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PDF CY7C10191B Data sheet ( Hoja de datos )
| Número de pieza | CY7C10191B | |
| Descripción | 128K x 8 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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C1019V33
CY7C1019B/
CY7C10191B
Features
• High speed
— tAA = 10, 12, 15 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Functionally equivalent to CY7C1019
Functional Description
The CY7C1019B/10191B is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
128K x 8 Static RAM
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location speci-
fied on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019B/10191B is available in standard 32-pin
TSOP Type II and 400-mil-wide SOJ packages. Customers
should use part number CY7C10191B when ordering parts
with 10 ns tAA, and CY7C1019B when ordering 12 and 15 ns
tAA.
ogic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE
WE
OE
INPUT BUFFER
512 x 256 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Pin Configurations
SOJ / TSOPII
Top View
A0 1
32 A16
A1 2
31 A15
A2 3
30 A14
I/O0
A3 4
29 A13
CE 5
28 OE
I/O1
I/O0 6
27 I/O7
I/O1 7
26 I/O6
I/O2
VCC 8
25 VSS
VSS 9
24 VCC
I/O3
I/O2 10
23 I/O5
I/O4
I/O3 11
WE 12
22 I/O4
21 A12
I/O5
A4 13
20 A11
A5 14
19 A10
I/O6
A6 15
18 A9
A7 16
17 A8
I/O7
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05026 Rev. *A
Revised August 13, 2002
1 page  
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[12, 13]
ADDRESS
CE
tSA
WE
DATA I/O
tWC
tSCE
tSCE
tAW
tPWE
tSD
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
CY7C1019B/
CY7C10191B
tHA
tHD
ADDRESS
CE
WE
tWC
tSCE
tAW
tSA tPWE
OE
DATA I/O
NOTE 14
tHZOE
tSD
DATAIN VALID
Notes:
12. Data I/O is high impedance if OE = VIH.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
tHA
tHD
Document #: 38-05026 Rev. *A
Page 5 of 9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY7C10191B.PDF ] | |
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