PDF CY7C1011BV33 Data sheet ( Hoja de datos )

Número de pieza	CY7C1011BV33
Descripción	128K x 16 Static RAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY7C1011BV33 Features • 3.0 – 3.6V Operation • High speed — tAA = 12, 15 ns • CMOS for optimum speed/power • Low active power — 684 mW (Max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in 44-pin TSOP II Functional Description The CY7C1011BV33 is a high-performance CMOS static RAM organized as 131,072 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable 128K x 16 Static RAM (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip En- able (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete descrip- tion of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1011BV33 is available in standard 44-pin TSOP Type II package. Logic Block Diagram DATA IN DRIVERS A7 A6 A5 128K x 16 A4 RAM Array A3 512 X 2048 A2 A1 A0 COLUMN DECODER I/O1–I/O8 I/O9–I/O16 BHE WE CE OE BLE 1011B-1 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-05021 Rev. A Revised June 6, 2001 1 page CY7C1011BV33 Switching Characteristics[5] Over the Operating Range Parameter WRITE CYCLE[8] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Description Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z[6, 7] Byte Enable to End of Write Switching Waveforms Read Cycle No. 1[9, 10] ADDRESS DATA OUT tOHA PREVIOUS DATA VALID tAA 1011BV33-12 Min. Max. 12 10 10 0 0 10 7 0 3 6 10 1011BV33-15 Min. Max. 15 12 12 0 0 12 8 0 3 7 12 tRC DATA VALID Unit ns ns ns ns ns ns ns ns ns ns ns 1011B-5 Note: 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for read cycle. Document #: 38-05021 Rev. A Page 5 of 10 5 Page

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