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PDF CY7C63201 Data sheet ( Hoja de datos )
| Número de pieza | CY7C63201 | |
| Descripción | Universal Serial Bus Microcontroller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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1CY 7C63 00 0
fax id: 3401
CY7C63000/CY7C63001
CY7C63100/CY7C63101
PRELIMINARY CY7C63200/CY7C63201
CY7C63000
CY7C63001
CY7C63100
CY7C63101
CY7C63200
CY7C63201
Universal Serial Bus Microcontroller
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 1996 - Revised June 26, 1997
1 page  
PRELIMINARY
CY7C63000/CY7C63001
CY7C63100/CY7C63101
CY7C63200/CY7C63201
.
Logic Block Diagram
6 MHz
RESONATOR
R/CEXT
OSC
AAAAAAAAAAAAAAAAAAAAIAAAAAAAAAANNAAAAAAAAAAAAAAAAAAAASOAAAAAAAAAATAAAAAAAAAAWAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA<NAAAAAAAAAATAAAAAAAAAATAAAAAAAAAAM-AAAAAAAAAAOAAAAAAAAAA>AAAAAAAAAANAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
RAM
128 Byte
8-bit
Timer
EPROM
2K/4K Byte
Power
on Reset
Watch
Dog
Timer
8-bit
RISC
core
Interrupt
Controller
USB
Engine
PORT
0
PORT
1
D+,D–
VCC/VSS
P0.0–P0.7
P1.0–P1.7
PinConfigurations (Top View)
18-pin
DIP/
Windowed CerDIP
P0.0
P0.1
P0.2
P0.3
P1.0
VSS
VPP
CEXT
XTALIN
1
2
3
4
5
6
7
8
9
18 P0.4
17 P0.5
16 P0.6
15 P0.7
14 P1.1
13 D+
12 D-
11 VCC
10 XTALOUT
20-pin
DIP/SOIC/
Windowed CerDIP
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
VSS
VPP
CEXT
XTALIN
1
2
3
4
5
6
7
8
9
10
20 P0.4
19 P0.5
18 P0.6
17 P0.7
16 P1.1
15 P1.3
14 D+
13 D-
12 VCC
11 XTALOUT
24-pin
SOIC/
Windowed CerDIP
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
VPP
CEXT
XTALIN
1
2
3
4
5
6
7
8
9
10
11
12
24 P0.4
23 P0.5
22 P0.6
21 P0.7
20 P1.1
19 P1.3
18 P1.5
17 P1.7
16 D+
15 D–
14 VCC
13 XTALOUT
6311–1
5
5 Page 
PRELIMINARY
CY7C63000/CY7C63001
CY7C63100/CY7C63101
CY7C63200/CY7C63201
5.3.2 Watch Dog Reset (WDR)
The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit of the 4-bit Watch Dog Timer Register transitions from
LOW to HIGH. Writing any value to the write-only Watch Dog Restart Register at 0x21 will clear the timer. The Watch Dog timer
is clocked by a 1.024 ms clock from the free running timer. If 8 clocks occur between writes to the timer, a WDR occurs. Bit 6 of
the Status and Control Register will be set to record the event. A Watch Dog Timer Reset lasts for 8.192 ms after which the
microcontroller begins execution at ROM address 0x00. The USB transmitter is disabled by a Watch Dog Reset because the
USB Device Address Register is cleared. Otherwise, the USB Controller would respond to all address 0 transactions. The
transmitter remains disabled until the WDR bit in the Status and Control Register is reset to 0 by firmware.
8.192 ms
8.192 ms
last write to
Watchdog Timer
Register
No write to WDT
register, so WDR
goes high
Execution begins at
Reset Vector 0X00
Figure 5-4. Watch Dog Reset (WDR)
5.3.3 USB Bus Reset
The USB Controller recognizes a USB Reset when a Single Ended Zero (SE0) condition persists for longer than 8 micro-seconds.
SE0 is defined as the condition in which both the D+ line and the D– line are LOW. Bit 5 of the Status and Control Register will
be set to record this event. If the USB reset happens while the device is suspended (such as after a POR), the suspend condition
will be cleared and the clock oscillator will be restarted. However, the microcontroller is not released until the USB reset is
removed.
5.4 On-chip Timer
The USB Controller is equipped with an 8-bit free-running timer driven by a clock one-sixth the crystal frequency. Bits 0 through
7 of the counter are readable from the read-only Timer Register located at I/O address 0x23. The Timer Register is cleared during
a Power-On Reset. Figure 5-5 illustrates the format of this register and Figure 5-6 is its block diagram.
With a 6 MHz crystal, the timer resolution is 1 µs.
The timer generates two interrupts: the 128 µs interrupt and the 1.024 ms interrupt.
7
R
Count 7
6
R
Count 6
5
R
Count 5
4
R
Count 4
3
R
Count 3
2
R
Count 2
Figure 5-5. Timer Register (Address 0x23)
1
R
Count 1
0
R
Count 0
11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet CY7C63201.PDF ] | |
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