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PDF CY7C4275-15ASC Data sheet ( Hoja de datos )
| Número de pieza | CY7C4275-15ASC | |
| Descripción | 32K/64Kx18 Deep Sync FIFOs | |
| Fabricantes | Cypress Semiconductor | |
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285
CY7C4275
CY7C4285
32K/64Kx18 Deep Sync FIFOs
Features
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
• 32K x 18 (CY7C4275)
• 64K x 18 (CY7C4285)
• 0.5 micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power
— ICC=50 mA
— ISB = 2 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• Depth Expansion Capability
• 68-pin PLCC and 64-pin 10x10 TQFP
• Pin-compatible density upgrade to CY7C42X5
families
• Pin-compatible density upgrade to
IDT72205/15/25/35/45
The CY7C4275/85 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4275/85 can
be cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and commu-
nications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4275/85 have an output
enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to 100
MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to VSS and the FL pin of all the remaining devic-
es should be tied to VCC.
Logic Block Diagram
D0 –17
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
WRITE
POINTER
RAM
ARRAY
32Kx18
64Kx18
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
READ
POINTER
FF
EF
PAE
PAF
SMODE
RS RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
THREE–STATE
OUTPUT REGISTER
Q0– 17
OE
READ
CONTROL
RCLK REN 4275–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06008 Rev. *A
Revised December 26, 2002
1 page  
CY7C4275
CY7C4285
AC Test Loads and Waveforms[9, 10]
5V
OUTPUT
R1 1.1KΩ
CL
INCLUDING
JIG AND
SCOPE
R2
680Ω
4275–4
3.0V
GND
≤ 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 3 ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
410Ω
1.91V
4275–5
Switching Characteristics Over the Operating Range
Parameter
Description
tS Clock Cycle Frequency
tA Data Access Time
tCLK Clock Cycle Time
tCLKH
Clock HIGH Time
tCLKL
Clock LOW Time
tDS Data Set-Up Time
tDH Data Hold Time
tENS
Enable Set-Up Time
tENH
tRS
Enable Hold Time
Reset Pulse Width[11]
tRSR
Reset Recovery Time
tRSF
Reset to Flag and Output Time
tPRT Retransmit Pulse Width
tRTR
tOLZ
Retransmit Recovery Time
Output Enable to Output in Low Z[12]
tOE
tOHZ
Output Enable to Output Valid
Output Enable to Output in High Z[12]
tWFF
Write Clock to Full Flag
tREF
tPAFasynch
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC)
tPAFsynch
tPAEasynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
Clock to Programmable Almost-Empty Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC)
Notes:
9. CL = 30 pF for all AC parameters except for tOHZ.
10. CL = 5 pF for tOHZ.
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
Document #: 38-06008 Rev. *A
7C42X5-10
Min. Max.
100
28
10
4.5
4.5
3
0.5
3
0.5
10
8
10
60
90
0
37
37
8
8
15
7C42X5-15
Min. Max.
66.7
2 10
15
6
6
4
1
4
1
15
10
15
60
90
0
38
38
10
10
16
7C42X5-25
Min. Max.
40
2 15
25
10
10
6
1
6
1
25
15
25
60
90
0
3 12
3 12
15
15
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8 10 15 ns
15 16 20 ns
Page 5 of 21
5 Page 
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
tCLKH
tCLKL
WCLK
WEN
tENS tENH
PAE
RCLK
REN
tSKEW3 [22]
Note 21
tPAE synch
N + 1 WORDS
IN FIFO
tENS
tENS tENH
CY7C4275
CY7C4285
Note 23 tPAE synch
Programmable Almost Full Flag Timing
4275–14
WCLK
WEN
tCLKH
Note 24
tCLKL
tENS tENH
PAF [25]
RCLK
REN
tPAF FULL– M WORDS
IN FIFO[26]
FULL– (M+1) WORDS
IN FIFO [27]
tPAF
tENS
4275–15
Notes:
21. PAE offset − n.
22. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
24. PAF offset = m. Number of data words written into FIFO already = 32768 − (m + 1) for the CY7C4285 and 65536 − (m + 1) for the CY7C4285.
25. PAF is offset = m.
26. 32768 − m words in CY7C4275 and 65536 – m words in CY7C4285.
27. 32768 − (m + 1) words in CY7C4275 and 65536 – (m + 1) CY7C4285.
Document #: 38-06008 Rev. *A
Page 11 of 21
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