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PDF CY7C344-25HMB Data sheet ( Hoja de datos )
| Número de pieza | CY7C344-25HMB | |
| Descripción | 32-Macrocell MAX EPLD | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C344B
32-Macrocell MAX® EPLD
Features
• High-performance, high-density replacement for TTL,
74HC, and custom logic
• 32 macrocells, 64 expander product terms in one LAB
• 8 dedicated inputs, 16 I/O pins
• 0.8-micron double-metal CMOS EPROM technology
• 28-pin, 300-mil DIP, cerDIP or 28-pin HLCC, PLCC
package
Functional Description
Available in a 28-pin, 300-mil DIP or windowed J-leaded
ceramic chip carrier (HLCC), the CY7C344 represents the
densest EPLD of this size. Eight dedicated inputs and 16
bidirectional I/O pins communicate to one logic array block. In
the CY7C344 LAB there are 32 macrocells and 64 expander
product terms. When an I/O macrocell is used as an input, two
expanders are used to create an input path. Even if all of the
I/O pins are driven by macrocell registers, there are still 16
“buried” registers available. All inputs, macrocells, and I/O pins
are interconnected within the LAB.
The speed and density of the CY7C344 makes it a natural for
all types of applications. With just this one device, the designer
can implement complex state machines, registered logic, and
combinatorial “glue” logic, without using multiple chips. This
architectural flexibility allows the CY7C344 to replace
multichip TTL solutions, whether they are synchronous,
asynchronous, combinatorial, or all three.
Logic Block Diagram[1]
15(22)
15(23)
27(6)
28(7)
INPUT
INPUT
INPUT
INPUT
MACROCELL 2
MACROCELL 4
MACROCELL 6
MACROCELL 8
MACROCELL 10
MACROCELL 12
MACROCELL 14
MACROCELL 16
MACROCELL 18
MACROCELL 20
MACROCELL 22
MACROCELL 24
MACROCELL 26
MACROCELL 28
MACROCELL 30
MACROCELL 32
G
L
O
B
A
L
B
U
S
INPUT
1(8)
INPUT/CLK 2(9)
INPUT
13(20)
INPUT
14(21)
MACROCELL 1
MACROCELL 3
MACROCELL 5
MACROCELL 7
MACROCELL 9
MACROCELL 11
MACROCELL 13
MACROCELL 15
MACROCELL 17
MACROCELL 19
MACROCELL 21
MACROCELL 23
MACROCELL 25
MACROCELL 27
MACROCELL 29
MACROCELL 31
I
O
C
O
N
T
R
O
L
64 EXPANDER PRODUCT TERM ARRAY
32
Pin Configurations
HLCC
Top View
I/O 3(10)
I/O 4(11)
I/O 5(12)
I/O 6(13)
I/O 9(16)
I/O 10(17)
I/O 11(18)
I/O 12(19)
I/O 17(24)
I/O 18(25)
I/O 19(26)
I/O 20(27)
I/O 23(2)
I/O 24(3)
I/O 25(4)
I/O 26(5)
I/O
INPUT
INPUT
INPUT
INPUT/CLK
I/O
I/O
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11
12 13 14 1516
1718 19
I/O
I/O
INPUT
INPUT
INPUT
INPUT
I/O
CerDIP
Top View
INPUT
INPUT/CLK
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
INPUT
INPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 INPUT
27 INPUT
26 I/O
25 I/O
24 I/O
23 I/O
22 VCC
21 GND
20 I/O
19 I/O
18 I/O
17 I/O
16 INPUT
15 INPUT
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03006 Rev. *A
Revised April 19, 2004
1 page  
USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C344B
External Synchronous Switching Characteristics Over Operating Range [7]
7C344-15 7C344-20 7C344-25
Parameter
tPD1
tPD2
Description
Dedicated Input to Combinatorial Output Delay[8]
I/O Input to Combinatorial Output Delay[9]
Com’l/Ind
Mil
Com’l/Ind
Mil
Min.
Max.
15
15
15
15
Min.
Max.
20
20
20
20
Min.
Max.
25
25
25
25
Unit
ns
ns
tPD3
Dedicated Input to Combinatorial Output Delay Com’l/Ind
with Expander Delay[10]
Mil
30
30
30
30
40 ns
40
tPD4
I/O Input to Combinatorial Output Delay with
Expander Delay[4, 11]
Com’l/Ind
Mil
30
30
30
30
40 ns
40
tEA Input to Output Enable Delay[4]
Com’l/Ind
20
20
25 ns
Mil 20 20 25
tER Input to Output Disable Delay[4]
Com’l/Ind
20
20
25 ns
Mil 20 20 25
tCO1
Synchronous Clock Input to Output Delay
Com’l/Ind
10
12
15 ns
Mil 10 12 15
tCO2
Synchronous Clock to Local Feedback to
Combinatorial Output[4, 12]
Com’l/Ind
Mil
20
20
22
22
29 ns
29
tS Dedicated Input or Feedback Set-Up Time to Com’l/Ind 10 12 15 ns
Synchronous Clock Input
Mil 10 12 15
tH Input Hold Time from Synchronous Clock Input[7] Com’l/Ind 0 0 0 ns
Mil 0 0 0
tWH Synchronous Clock Input HIGH Time[4]
Com’l/Ind 6
7
8 ns
Mil 6 7 8
tWL Synchronous Clock Input LOW Time[4]
Com’l/Ind 6
7
8 ns
Mil 6 7 8
tRW Asynchronous Clear Width[4]
Com’l/Ind 20 20 25 ns
Mil 20 20 25
tRR Asynchronous Clear Recovery Time[4] Com’l/Ind 20 20 25 ns
Mil 20 20 25
tRO
Asynchronous Clear to Registered Output
Delay[4]
Com’l/Ind
Mil
15
15
20
20
25 ns
25
tPW Asynchronous Preset Width[4]
Com’l /Ind 20 20 25 ns
Mil 20 20 25
tPR Asynchronous Preset Recovery Time[4]
Com’l /Ind 20
20
25
ns
Mil 20 20 25
Notes:
8. This parameter is the delay from an input signal applied to a dedicated input pin to a combinatorial output on any output pin. This delay assumes no expander
terms are used to form the logic function.
9. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This parameter is the delay associated with an input signal applied to a dedicated input pin to combinatorial output on any output pin. This delay assumes
expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter
is tested periodically by sampling production material.
11. This parameter is the delay associated with an input signal applied to an I/O macrocell pin to any output pin. This delay assumes expander terms are used to
form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
12. This specification is a measure of the delay from synchronous register clock input to internal feedback of the register output signal to a combinatorial output for
which the registered output signal is used as an input. This parameter assumes no expanders are used in the logic of the combinatorial output and the register
is synchronously clocked. This parameter is tested periodically by sampling production material.
Document #: 38-03006 Rev. *A
Page 5 of 16
5 Page 
USE ULTRA37000TM FOR
ALL NEW DESIGNS
Switching Waveforms (continued)
Internal Asynchronous
tIOtR
CLOCK PIN
CLOCK INTO
LOGIC ARRAY
CLOCK FROM
LOGIC ARRAY
DATA FROM
LOGIC ARRAY
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
tAWH
tIN
tAWL
tIC
tRSU
tRH
tRD,tLATCH
tFD
REGISTER OUTPUT
TO ANOTHER LAB
tF
tPIA
tCLR,tPRE
CY7C344B
tFD
Internal Synchronous (Input Path)
SYSTEM CLOCK PIN
tCH
SYSTEM CLOCK
AT REGISTER
DATA FROM
LOGIC ARRAY
tIN
tRSU
tICS
tRH
Internal Synchronous (Output Path)
CLOCK FROM
LOGIC ARRAY
tRD
DATA FROM
LOGIC ARRAY
tOD
OUTPUT PIN
tCL
tXZ tZX
HIGH Z
Document #: 38-03006 Rev. *A
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CY7C344-25HMB.PDF ] | |
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