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PDF LTC7652 Data sheet ( Hoja de datos )

Número de pieza LTC7652
Descripción Zero-Drift Operational Amplifier
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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LTC1052/LTC7652
Zero-Drift
Operational Amplifier
FEATURES
Guaranteed Max Offset: 5µV
Guaranteed Max Offset Drift: 0.05µV/°C
Typ Offset Drift: 0.01µV/°C
Excellent Long Term Stability: 100nV/Month
Guaranteed Max Input Bias Current: 30pA
Over Operating Temperature Range:
Guaranteed Min Gain: 120dB
Guaranteed Min CMRR: 120dB
Guaranteed Min PSRR: 120dB
Single Supply Operation: 4.75V to 16V
(Input Voltage Range Extends to Ground)
External Capacitors can be Returned to Vwith No
Noise Degradation
U
APPLICATIO S
Thermocouple Amplifiers
Strain Gauge Amplifiers
Low Level Signal Processing
Medical Instrumentation
DESCRIPTIO
The LTC®1052 and LTC7652 are low noise zero-drift op
amps manufactured using Linear Technology’s enhanced
LTCMOSTM silicon gate process. Chopper-stabilization
constantly corrects offset voltage errors. Both initial offset
and changes in the offset due to time, temperature and
common mode voltage are corrected. This, coupled with
picoampere input currents, gives these amplifiers
unmatched performance.
Low frequency (1/f) noise is also improved by the
chopping technique. Instead of increasing continuously
at a 3dB/octave rate, the internal chopping causes noise to
decrease at low frequencies.
The chopper circuitry is entirely internal and completely
transparent to the user. Only two external capacitors
are required to alternately sample-and-hold the offset
correction voltage and the amplified input signal. Control
circuitry is brought out on the 14-pin and 16-pin versions
to allow the sampling of the LTC1052 to be synchronized
with an external frequency source.
, LTC and LT are registered trademarks of Linear Technology Corporation.
LTCMOS is a trademark of Linear Technology Corporation.
Teflon is a trademark of DuPont.
TYPICAL APPLICATIO
INPUT
Ultralow Noise, Low Drift Amplifier
5V
3+ 7
LTC1052
24
1
0.1µF
6
8
0.1µF
–5V
0.1µF
5V
100k
3K
1 5V 68k
3+ 7
8
LT®1007
24
6
– 5V
VOS = 3µV
VOST = 50nV/°C
NOISE = 0.06µVP-P 0.1Hz TO 10Hz
1.5k
5V
OUTPUT
100k
100
LTC1052/7652 • TA01
160
140
120
100
80
60
40
20
0
0
Noise Spectrum
100 200 300 400 500
FREQUENCY (Hz)
LTC1052/7652 • TA02
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LTC7652 pdf
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1052/LTC7652
Broadband Noise, CEXT = 0.1µF
AV = – 1000
1ms/DIV
Supply Current vs Supply Voltage
2.5
2.0
1.5
1.0
0.5
0
4 5 6 8 10 12 14 16
TOTAL SUPPLY VOLTAGE, V+ TO V(V)
LTC1052/LTC7652 • TPC08
Sampling Frequency vs Voltage
600
TA = 25°C
500
400
300
200
100
0
4 5 6 8 10 12 14 16
TOTAL SUPPLY VOLTAGE, V+ TO V(V)
LTC1052/LTC7652 • TPC11
Broadband Noise, CEXT = 1.0µF
AV = –1000
1ms/DIV
Supply Current vs Temperature
3.0
SUPPLY VOLTAGE = ± 5V
2.0
1.0
0
–50 –25 0 25 50 75 100 125
AMBIENT TEMPERATURE, TA (°C)
LTC1052/LTC7652 • TPC09
Sampling Frequency vs
Temperature
600
SUPPLY VOLTAGE = ± 5V
500
400
300
200
100
0
– 50 – 25 0 25 50 75 100
AMBIENT TEMPERATURE, TA (°C)
125
LT1052/LTC7652 • TPC12
Broadband Noise Test Circuit (TC2)
R2
1M
R1 5V
1k 2 7
R3
1k
LTC1052
3+ 4
1
CEXTA
6
8
CEXTB
– 5V
LTC1052/7652 • TPC07
Output Short-Circuit Current vs
Supply Voltage
8
6
4 ISOURCE VOUT = V
2
0
– 10
– 20 ISINK VOUT = V+
– 30
456
8 10 12 14 16
TOTAL SUPPLY VOLTAGE, V+ TO V(V)
LTC1052/LTC7652 • TPC10
Comparator Operation
VREF*
VIN
1k
25
5V
7
6
1k
LTC1052
3+
8
4
1
0.1µF
0.1µF
* – 5V VREF 2.7 V
– 5V
LTC1052/7652 • TPC13
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LTC7652 arduino
APPLICATIO S I FOR ATIO
#1 COVERED
1µV
#1 UNCOVERED
LTC1052/LTC7652
#2 UNCOVERED
20 SEC
Figure 5. DC to 1Hz (Test Circuit TC3)
PACKAGE-INDUCED OFFSET VOLTAGE
Since the LTC1052 is constantly fixing its own offset, it
may be asked why there is any error at all, even under
transient temperature conditions. The answer is simple.
The LTC1052 can only fix offsets inside its own nulling
loop. There are many thermal junctions outside this loop
that cannot be distinguished from legitimate signals.
Some have been discussed previously, but the package
thermal EMF effects are an important source of errors.
Notice the difference in the thermal response curves of
Figure 4. This can only be attributed to the package since
everything else is identical. In fact, the VOS specification is
set by the package-induced warm-up drift, not by the
LTC1052. TO-99 metal cans exhibit the worst warm-up
drift and Linear Technology sample tests TO-99 lots to
minimize this problem.
Two things make 100% screening costly: (1) The extreme
precision required on the LTC1052 and (2) the thermal
time constant of the package is 0.5 to 3 minutes, depend-
ing on package type. The first precludes the use of auto-
matic handling equipment and the second takes a long
time. Bench test equipment is available to 100% test for
warmed-up drift if offsets of less than ±5µV are required.
CLOCK
The LTC1052 has an internal clock, setting the nominal
sampling frequency at 330Hz. On 8-pin devices, there is
no way to control the clock externally. In some applica-
tions it may be desirable to control the sampling clock and
this is the function of the 14-pin device.
CLK IN, CLK OUT and INT/EXT are provided to accomplish
this. With no external connection, an internal pull-up holds
INT/EXT at the V+ supply and the 14-pin device self-
oscillates at 330Hz. In this mode there is a signal on the
CLK IN pin of 660Hz (2 times sampling frequency) with a
30% duty cycle. A divide-by-two drives the CLK OUT pin
and sets the sampling frequency.
To use an external clock, connect INT/EXT to Vand the
external clock to CLK IN. The logic threshold of CLK IN is
2.5V below the positive supply; this allows CMOS logic to
drive it directly with logic supplies of V+ and ground. CLK
IN can be driven from V+ to Vif desired. The duty cycle of
the external clock is not particularly critical but should be
kept between 30% and 60%.
Capacitance between CLK IN and CLK OUT (pins 13 and
12) can cause the divide-by-two circuit to malfunction. To
avoid this, keep this capacitance below 5pF.
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