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PDF LTC3701 Data sheet ( Hoja de datos )
| Número de pieza | LTC3701 | |
| Descripción | 2-Phase/ Low Input Voltage/ Dual Step-Down DC/DC Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC3701
2-Phase, Low Input Voltage,
Dual Step-Down DC/DC Controller
FEATURES
s Out-of-Phase Controllers Reduce Required
Input Capacitance
s True PLL for Frequency Locking or Frequency
Adjustment
s Operating Frequency Range: 300kHz to 750kHz
s Wide VIN Range: 2.5V to 10V
s Constant Frequency Current Mode Architecture
s Low Dropout: 100% Duty Cycle
s Power Good Output Voltage Monitor
s Internal Soft-Start Circuitry
s Selectable Burst Mode®/Pulse Skipping Operation
at Light Loads
s Output Overvoltage Protection
s Low Quiescent Current: 460µA
s 0.8V ±2% Voltage Reference
s Small 16-Lead Narrow SSOP Package
U
APPLICATIO S
s One or Two Lithium-Ion Powered Applications
s Notebook and Handheld Computers
s Personal Digital Assistants
s Portable Instruments
s Distributed DC Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
DESCRIPTIO
The LTC®3701 is a 2-phase dual constant frequency cur-
rent mode step-down DC/DC controller providing excellent
load and line regulation. Power loss and noise due to ESR
of the input capacitor are minimized by operating the two
controller output stages out-of-phase.
The LTC3701 provides a 0.8V ±2% voltage reference and
consumes only 460µA of quiescent current. To further
maximize the life of a battery source, the external
P-channel MOSFET is turned on continuously in dropout
(100% duty cycle).
Switching frequency is internally set at 550kHz, allowing
the use of small inductors and capacitors. For noise sen-
sitive applications, the LTC3701 can be externally syn-
chronized using its phase-locked loop. The frequency can
also be externally set from 300kHz to 750kHz by applying
a voltage to the PLLLPF pin. Burst Mode operation is inhib-
ited during synchronization or when the EXTCLK/MODE
pin is pulled low to reduce noise and RF interference.
The LTC3701 contains independent internal soft-start
circuitry for each controller. Other features include a
power good output voltage monitor and output overvolt-
age and short-circuit protection.
The LTC3701 is available in a small footprint 16-lead nar-
row SSOP package.
TYPICAL APPLICATIO
169k
78.7k
220pF
10k
80.6k
10k
220pF
100k
1 SENSE1–
SENSE1+ 16
3
VFB1
15
VIN
2
ITH/RUN1
14
PGATE1
4 SGND LTC3701 PGND 13
6
ITH/RUN2
PGATE2 12
5
VFB2
PGOOD 11
7 10
PLLLPF EXTCLK/MODE
8 SENSE2–
SENSE2+ 9
0.03Ω
M1
M2
0.03Ω
VIN
2.5V TO 9.8V
L1
4.7µH +
D1
47µF
VOUT1
2.5V
2A
10µF
D2
L2
4.7µH
47µF
VOUT2
1.8V
2A
D1, D2: IR10BQ015 L1, L2: LQN6C-4R7 M1, M2: FDC638P
3701 F01a
Figure 1. High Efficiency 2-Phase 550kHz Dual Step-Down Converter
Efficiency vs Load Current
100
VIN = 4.2V VIN = 3.3V
90
80
VIN = 6V
70 VIN = 8.4V
60
50
40
1
VOUT = 2.5V
10 100 1000
LOAD CURRENT (mA)
10000
3701 F01b
3701fa
1
1 page  
LTC3701
PI FU CTIO S
SENSE1–, SENSE2– (Pins 1, 8): The (–) Inputs to the
Differential Current Comparators.
ITH/RUN1, ITH/RUN2 (Pins 2, 6): These pins each serve
two functions. Each pin serves as the error amplifier
compensation point as well as the run control input for the
respective controller. Forcing one pin below 0.35V causes
the functions associated with that controller to be shut
down. Forcing both ITH/RUN pins below 0.35V causes the
device to be shut down. Nominal operating voltage range
on these pins is from 0.7V to 1.9V.
VFB1, VFB2 (Pins 3, 5): Each receives the remotely sensed
feedback voltage for each controller from an external
resistive divider across the output.
SGND (Pin 4): Signal Ground.
PLLLPF (Pin 7): Serves as the lowpass filter point for the
PLL and as the voltage control input to the internal
oscillator. Normally, a series RC is connected between this
pin and ground when synchronizing to an external clock.
Nominal voltage range is from 0V to 2.4V. Frequency can
be set by forcing this pin with a voltage. Tying this pin to
GND selects 300kHz. Tying to VIN or a voltage ≥ 2.4V
selects 750kHz. Floating this pin selects 550kHz opera-
tion.
SENSE2+ (PVIN2), SENSE1+ (PVIN1) (Pins 9, 16): The (+)
Inputs to the Differential Current Comparators. These pins
also power the gate drivers.
EXTCLK/MODE (Pin 10): External Clock Input. Applying a
clock to this pin causes the internal oscillator to phase-
lock to the external clock (nominal lock frequency range
between 300kHz and 750kHz). This also disables Burst
Mode operation but allows pulse-skipping at low load
currents.
Forcing this pin high enables Burst Mode operation.
Forcing this pin low enables pulse-skipping mode. In
these cases, the frequency of the internal oscillator is set
by the voltage on the PLLLPF pin. If the PLLLPF voltage is
not set externally, the frequency internally defaults to
550kHz.
PGOOD (Pin 11): Power Good Output Voltage Monitor
Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (VFB1, VFB2) is not
within ±8% of its nominal set point. PGOOD is pulled low
when channel 1 or both channels are shut down. When
channel 2 is shut down and channel 1 enabled, the
PGOOD output indicates the state of VFB1 only.
PGATE2, PGATE1 (Pins 12, 14): Gate Drivers for the
External P-Channel MOSFETs. These pins swing from 0 to
SENSE+ (PVIN).
PGND (Pin 13): Ground Pin for Gate Drivers.
VIN (Pin 15): Chip Signal Power Supply Input. This pin
powers the entire chip except for the gate drivers.
3701fa
5
5 Page 
LTC3701
APPLICATIO S I FOR ATIO
size for a fixed inductor value, but is very dependent on the
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will in-
crease. Ferrite designs have very low core losses and are
preferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when several layers of wire can be used, while
inductors wound on bobbins are generally easier to sur-
face mount. However, new designs for surface mount that
do not increase the height significantly are available from
Coiltronics, Coilcraft, Dale and Sumida.
Power MOSFET Selection
An external P-channel MOSFET must be selected for use
with each channel of the LTC3701. The main selection
criteria for the power MOSFET are the threshold voltage
VGS(TH), “on” resistance RDS(ON), reverse transfer capaci-
tance CRSS and the total gate charge.
Since the LTC3701 is designed for operation down to low
input voltages, a sublogic level threshold MOSFET (RDS(ON)
guaranteed at VGS = 2.5V) is required for applications that
work close to this voltage. When these MOSFETs are used,
make sure that the input supply to the LTC3701 is less than
the absolute maximum MOSFET VGS rating, typically 8V.
The required minimum RDS(ON) of the MOSFET is gov-
erned by its allowable power dissipation. For applications
that may operate the LTC3701 in dropout, i.e., 100% duty
cycle, the required RDS(ON) is given by:
( ) ( )RDS(ON)DC=100% =
PP
IOUT(MAX) 2
1+ δp
where PP is the allowable power dissipation and δp is the
temperature dependency of RDS(ON) . (1 + δp) is generally
given for a MOSFET in the form of a normalized RDS(ON) vs
temperature curve, but δp = 0.005/°C can be used as an
approximation for low voltage MOSFETs.
In applications where the maximum duty cycle is less than
100% and the LTC3701 is in continuous mode, the RDS(ON)
is governed by:
RDS(ON)
≅
PP
(DC)IOUT2(1+
δp)
where DC is the maximum operating duty cycle for that
channel of the LTC3701.
Output Diode Selection
The catch diode carries load current during the switch off-
time. The average diode current is therefore dependent on
the P-channel MOSFET duty cycle. At high input voltages,
the diode conducts most of the time. As VIN approaches
VOUT, the diode conducts for only a small fraction of the
time. The most stressful condition for the diode is when
the output is short-circuited. Under this condition, the
diode must safely handle IPEAK at close to 100% duty
cycle. Therefore, it is important to adequately specify the
diode peak current and average power dissipation so as
not to exceed the diode’s ratings.
Under normal load conditions, the average current con-
ducted by the diode is:
ID
=
VIN – VOUT
VIN + VD
IOUT
The allowable forward voltage drop in the diode is calcu-
lated from the maximum short-circuit current as:
VF
≈
PD
IPEAK
where PD is the allowable power dissipation and will be
determined by efficiency and/or thermal requirements.
A Schottky diode is a good choice for low forward drop and
fast switching time. Remember to keep lead length short
and observe proper grounding (see Board Layout Check-
list) to avoid ringing and increased dissipation.
3701fa
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC3701.PDF ] | |
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