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PDF LTC2404C Data sheet ( Hoja de datos )
| Número de pieza | LTC2404C | |
| Descripción | 4-/8-Channel 24-Bit uPower No Latency ADCs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s Pin Compatible 4-/8-Channel 24-Bit ADCs
s Single Conversion Digital Filter Settling Time
Simplifies Multiplexing
s 4ppm INL, No Missing Codes
s 4ppm Full-Scale Error
s 0.5ppm Offset
s 0.3ppm Noise
s Internal Oscillator—No External Components
Required
s 110dB Min, 50Hz/60Hz Notch Filter
s Reference Input Voltage: 0.1V to VCC
s Live Zero—Extended Input Range Accommodates
12.5% Overrange and Underrange
s Single Supply 2.7V to 5.5V Operation
s Low Supply Current (200µA) and Auto Shutdown
U
APPLICATIO S
s Weight Scales
s Direct Temperature Measurement
s Gas Analyzers
s Strain-Gage Transducers
s Instrumentation
s Data Acquisition
s Industrial Process Control
s 6-Digit DVMs
LTC2404/LTC2408
4-/8-Channel 24-Bit µPower
No Latency ∆ΣTM ADCs
DESCRIPTIO
The LTC®2404/LTC2408 are 4-/8-channel 2.7V to 5.5V
micropower 24-bit A/D converters with an integrated
oscillator, 4ppm INL and 0.3ppm RMS noise. They use
delta-sigma technology and provide single cycle digital
filter settling time (no latency delay) for multiplexed
applications. The first conversion after the channel is
changed is always valid. Through a single pin the LTC2404/
LTC2408 can be configured for better than 110dB rejec-
tion at 50Hz or 60Hz ±2%, or can be driven by an external
oscillator for a user defined rejection frequency in the
range 1Hz to 120Hz. The internal oscillator requires no
external frequency setting components.
The converters accept any external reference voltage from
0.1V to VCC. With their extended input conversion range of
–12.5% VREF to 112.5% VREF the LTC2404/LTC2408
smoothly resolve the offset and overrange problems of
preceding sensors or signal conditioning circuits.
The LTC2404/LTC2408 communicate through a flexible
4-wire digital interface which is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
TYPICAL APPLICATIO
0.1V TO VCC
2.7V TO 5.5V
ANALOG
INPUTS
–0.12VREF TO
1.12VREF
74
3 2, 8
MUXOUT
9 CH0
10 CH1
11 CH2
12 CH3
4-/8-CHANNEL
13 CH4*
MUX
14 CH5*
15 CH6*
17 CH7*
6 COM
ADCIN VREF VCC
24-BIT
+ ∆∑ ADC
–
CSADC
CSMUX
SCK
CLK
DIN
SDO
23
20
19
25
21
24
LTC2404/LTC2408
GND
26
FO
1, 5, 16, 18, 22, 27, 28
2404/08 TA01
*THESE PINS ARE NO CONNECTS ON THE LTC2404
1µF
SERIAL DATA LINK
MICROWIRE AND
SPI COMPATABLE
MPU
VCC
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
Total Unadjusted Error vs Output Code
10
8
VDD = 5V
VREF = 5V
6 TA = 25°C
FO = LOW
4
2
0
–2
–4
–6
–8
–10
0
8,338,608
OUTPUT CODE (DECIMAL)
16,777,215
2404/08 TA02
1
1 page  
LTC2404/LTC2408
WU
TI I G CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
fEOSC
tHEO
tLEO
tCONV
fISCK
DISCK
fESCK
tLESCK
tHESCK
tDOUT_ISCK
tDOUT_ESCK
t1
t2
t3
t4
tKQMAX
tKQMIN
t5
t6
PARAMETER
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
Internal SCK Frequency
Internal SCK Duty Cycle
External SCK Frequency Range
External SCK Low Period
External SCK High Period
Internal SCK 32-Bit Data Output Time
External SCK 32-Bit Data Output Time
CS ↓ to SDO Low Z
CS ↑ to SDO High Z
CS ↓ to SCK ↓
CS ↓ to SCK ↑
SCK ↓ to SDO Valid
SDO Hold After SCK ↓
SCK Set-Up Before CS ↓
SCK Hold After CS ↓
CONDITIONS
FO = 0V
FO = VCC
External Oscillator (Note 11)
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
(Note 10)
(Note 9)
(Note 9)
(Note 9)
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
(Note 9)
(Note 10)
(Note 9)
(Note 5)
MIN TYP MAX UNITS
q 2.56
307.2
kHz
q 0.5
390 µs
q 0.5
390 µs
q 130.66 133.33 136
q 156.80
160 163.20
q 20480/fEOSC (in kHz)
19.2
fEOSC/8
45 55
ms
ms
ms
kHz
kHz
%
q 2000 kHz
q 250
ns
q 250
ns
q 1.64
1.67 1.70
q 256/fEOSC (in kHz)
q 32/fESCK (in kHz)
q0
150
ms
ms
ms
ns
q0
150 ns
q0
150 ns
q 50
ns
q 200 ns
q 15
ns
q 50
ns
q 50 ns
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7 to 5.5V unless otherwise specified, source input
is 0Ω.
Note 4: Internal Conversion Clock source with the FO pin tied
to GND or to VCC or to external conversion clock source with
fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: For reference voltage values VREF > 2.5V the extended input
of – 0.125 • VREF to 1.125 • VREF is limited by the absolute maximum
rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF ≤
0.267V + 0.89 • VCC the input voltage range is – 0.3V to 1.125 • VREF.
For 0.267V + 0.89 • VCC < VREF ≤ VCC the input voltage range is – 0.3V
to VCC + 0.3V.
Note 15: VS is the voltage applied to a channel input. VD is the voltage
applied to the MUX output.
5
5 Page 
LTC2404/LTC2408
APPLICATIONS INFORMATION
Converter Operation Cycle
The LTC2404/LTC2408 are low power, 4-/8-channel delta-
sigma analog-to-digital converters with easy-to-use
4-wire interfaces. Their operation is simple and made up
of four states. The converter operation begins with the
conversion, followed by a low power sleep state and
concluded with the data output (see Figure 1). Channel
selection may be performed while the device is in the sleep
state or at the conclusion of the data output state. The
interface consists of serial data output (SDO), serial clock
(CLK/SCK), chip select (CSADC/CSMUX) and data input
(DIN). By tying SCK to CLK and CSADC to CSMUX, the
interface requires only four wires.
Initially, the LTC2404 or LTC2408 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, power consumption
is reduced by an order of magnitude. The part remains in
the sleep state as long as CSADC is logic HIGH. The
conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
Channel selection for the next conversion cycle is per-
formed while the device is in the sleep state or at the end
of the data output state. A specific channel is selected by
applying a 4-bit serial word to the DIN pin on the rising edge
of CLK while CSMUX is HIGH, see Figure 3 and Table 3. The
channel is selected based on the last four bits clocked into
the DIN pin before CSMUX goes low. If DIN is all 0’s, the
previous channel remains selected.
In the example, Figure 3, the MUX channel is selected
during the sleep state, just before the data output state
begins. Once the channel selection is complete, the device
remains in the sleep state as long as CSADC remains
HIGH.
Once CSADC is pulled low, the device begins outputting
the conversion result. There is no latency in the conversion
result. Since there is no latency, the first conversion
following a change in input channel is valid and corre-
sponds to that channel. The data output corresponds to
the conversion just performed. This result is shifted out on
the serial data output pin (SDO) under the control of the
serial clock (SCK). Data is updated on the falling edge of
SCK allowing the user to reliably latch data on the rising
CONVERT
CHANNEL SELECT
(SLEEP)
SLEEP
1 CSADC
AND
SCK
0
DATA OUTPUT
(CHANNEL SELECT)
24048 F01
Figure 1. LTC2408 State Transition Diagram
edge of SCK, see Figure 3. The data output state is
concluded once 32 bits are read out of the ADC or when
CSADC is brought HIGH. The device automatically initiates
a new conversion and the cycle repeats.
Through timing control of the CSADC and SCK pins, the
LTC2404/LTC2408 offer two modes of operation: internal
or external SCK. These modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage delta-sigma converters offer over
conventional type converters is an on-chip digital filter
(commonly known as Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typi-
cally designed to reject line frequencies of 50 or 60Hz plus
their harmonics. In order to reject these frequencies in
excess of 110dB, a highly accurate conversion clock is
required. The LTC2404/LTC2408 incorporate an on-chip
highly accurate oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2404/
LTC2408 reject line frequencies (50 or 60Hz ±2%) a
minimum of 110dB.
11
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet LTC2404C.PDF ] | |
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