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PDF LTC1753CG Data sheet ( Hoja de datos )
| Número de pieza | LTC1753CG | |
| Descripción | 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium III Processor | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
s 5-Bit Digitally Programmable 1.3V to 3.5V Fixed
Output Voltage, VRM 8.4 Compliant
s Fast Transient Response: 0% to 100% Duty Cycle
s Phase Lead Compensation for Remote Sensing
s Overtemperature Protection
s Flags for Power Good and Overvoltage Fault
s 19A Output Current Capability from a 5V Supply
s Dual N-Channel MOSFET Synchronous Driver
s Initial Output Accuracy: ±1.5%
s Excellent Output Accuracy: ±2% Typ Over Line,
Load and Temperature Variations
s High Efficiency: Over 95% Possible
s Adjustable Current Limit Without External Sense
Resistors
s Available in 2O-Lead SSOP and SW Packages
U
APPLICATIO S
s Power Supply for Pentium® III, AMD-K6®-2, SPARC,
ALPHA and PA-RISC Microprocessors
s High Power 5V to 1.3V-3.5V Regulators
LTC1753
5-Bit Programmable
Synchronous Switching
Regulator Controller for
Pentium® III Processor
DESCRIPTIO
The LTC®1753 is a high power, high efficiency switching
regulator controller optimized for 5V input to a digitally
programmable 1.3V-3.5V output. The internal 5-bit DAC
programs the output voltage from 1.3V to 2.05V in 50mV
increments and from 2.1V to 3.5V in 100mV increments. The
precision internal reference and an internal feedback system
provide an output accuracy of ±1.5% at room temperature
and typically ±2% over temperature, load current and line
voltage shifts. The LTC1753 uses a synchronous switching
architecture with two external N-channel output devices,
providing high efficiency and eliminating the need for a high
power, high cost P-channel device. Additionally, it senses the
output current across the on-resistance of the upper N-
channel FET, providing an adjustable current limit without an
external low value sense resistor.
The LTC1753 free-runs at 300kHz and can be synchronized
to a faster external clock if desired. It provides a phase lead
compensation scheme and under harsh loading conditions,
the PWM duty cycle can be momentarily forced to 0% or
100% to reduce the output voltage recovery time.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Pentium is a registered trademark of Intel Corporation.
AMD-K6 is a registered trademark of Advanced Micro Devices, Inc.
TYPICAL APPLICATIO
PVCC
12V
VIN
5V
5.6k 5.6k
+
0.1µF
10µF
600Ω 0.1µF
+
10µF
+ CIN**
1200µF
×4
Q1A*
PWRGD
VCC IMAX PVCC G1
Q1* LO†
1.3µH
FAULT
CPU 5
20Ω
IFB
18A
VID0 TO VID4
OUTEN
LTC1753
Q2A*
+COUT††
2700µF
G2 Q2* × 5
C1
150pF
RC
15k
CC
4700pF
COMP SS
CSS
0.1µF
SGND GND SENSE VFB
1µF
NC
* SILICONIX SUD50N03-10
** SANYO 10MV1200GX
† PANASONIC ETQP 6FIR3LFA
†† SANYO 6MV2700GX
Figure 1. 5V to 1.3V-3.5V Supply Application
VOUT
1.3V TO
3.5V
14A
1753 F01
1
1 page  
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency
vs Temperature
350
340
330
320
310
300
290
280
270
260
250
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
1753 G10
VCC Operating Supply Current
vs Temperature
1.2
VCC = 5V
1.1 fOSC = 300kHz
1.0
0.9
0.8
0.7
0.6
0.5
– 50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
1753 G13
IMAX Sink Current
vs Temperature
220
210
200
190
180
170
160
150
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
1753 G11
VCC Shutdown Supply Current
vs Temperature
250
225
200
175
150
125
100
75
50
– 50 – 25
0 25 50 75
TEMPERATURE (°C)
100 125
1753 G14
LTC1753
Soft-Start Source Current
vs Temperature
–8
–9
– 10
– 11
– 12
– 13
– 14
– 15
– 16
– 50 – 25
0 25 50 75
TEMPERATURE (°C)
100 125
1753 G12
PVCC Supply Current
vs Gate Capacitance
70
PVCC = 12V
60 TA = 25°C
50
40
30
20
10
0
0
2000
4000
6000
8000
GATE CAPACITANCE (pF)
1753 G15
Output Over Current Protection
3.0
2.5 Q1 CASE = 90°C, VOUT = 2.8V
Q1 = 2 × MTD20N03HDL
Q2 = 1 × MTD20N03HDL
2.0 RIMAX = 2.7k, RIFB = 20Ω,
SS CAP = 0.01µF
1.5
1.0
SHORT-CIRCUIT
CURRENT
0.5
0
02
4 6 8 10 12 14 16 18
OUTPUT CURRENT (A)
1753 G16
Transient Response, VOUT = 2.8V
VOUT
50mV/DIV
10
ILOAD
5A/DIV
0
50µs/DIV
1753 G17
5
5 Page 
LTC1753
APPLICATIO S I FOR ATIO
conventional TTL enable signal. The free-running 300kHz
PWM frequency can be synchronized to a faster external
clock connected to OUTEN. Adjusting the oscillator fre-
quency can add flexibility in the external component
selection. See the Clock Synchronization section.
Output regulation can be monitored with the PWRGD pin
which in turn monitors the internal MIN and MAX com-
parators. If the output is ±3% beyond the selected value
for more than 500µs, the PWRGD output will be pulled
low. Once the output has settled within ±3% of the se-
lected value for more than 1ms, PWRGD will return high.
THEORY OF OPERATION
Primary Feedback Loop
The regulator output voltage at the SENSE pin is divided
down internally by a resistor divider with a total resistance
of approximately 108k. This divided down voltage is
subtracted from a reference voltage supplied by the DAC
output. The resulting error voltage is amplified by the error
amplifier and the output is compared to the oscillator ramp
waveform by the PWM comparator. This PWM signal
controls the external MOSFETs through G1 and G2. The
resulting chopped waveform is filtered by LO and COUT
closing the loop. Loop frequency compensation is achieved
with an external RC + C network at the COMP pin, which is
connected to the output node of the transconductance
amplifier. In low output ripple voltage applications, low
ESR output capacitors are typically used. Under this
condition, a capacitor between the SENSE and VFB pins
helps compensate the switching loop. For heavy transient
output loading applications, a small capacitor between the
SENSE and VFB pin acts as a feedforward path and helps
reduce the transient recovery time.
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide
high speed fault correction in situations where the ERR
amplifier may not respond quickly enough. MIN compares
the feedback signal VFB to a voltage 3% below the internal
reference. If VFB is lower than the threshold of this com-
parator, the MIN comparator overrides the ERR
amplifier and forces the loop to 100% duty cycle.
Similarly, the MAX comparator forces the output to 0%
duty cycle if VFB is more than 3% above the internal
reference. To prevent these two comparators from trig-
gering due to noise, output voltage ripple must be controlled
with sufficient output bypassing to prevent jitter. In addi-
tion, the MIN and MAX comparators’ response times are
deliberately controlled so that they take about one micro-
second to respond. These two comparators help prevent
extreme output perturbations with fast output transients,
while allowing the main feedback loop to be optimally
compensated for stability.
Soft-Start and Current Limit
The LTC1753 includes a soft-start circuit which is used for
initial start-up and during current limit operation. The SS
pin requires an external capacitor to GND with the value
determined by the required soft-start time. An internal
12µA current source is included to charge the external SS
capacitor. During start-up, the COMP pin is clamped to a
diode drop above the voltage at the SS pin. This prevents
the error amplifier, ERR, from forcing the loop to 100%
duty cycle. The LTC1753 will begin to operate at low duty
cycle as the SS pin rises above about 1.2V (VCOMP ≈ 1.8V).
As SS continues to rise, QSS turns off and the error
amplifier begins to regulate the output. The MIN compara-
tor is disabled when soft-start is active to prevent it from
overriding the soft-start function.
The LTC1753 includes yet another feedback loop to con-
trol operation in current limit. Just before every falling
edge of G1, the current comparator, CC, samples and
holds the voltage drop measured across the external
MOSFET, Q1, at the IFB pin. CC compares the voltage at IFB
to the voltage at the IMAX pin. As the peak current rises, the
measured voltage across Q1 increases due to the drop
across the RDS(ON) of Q1. When the voltage at IFB drops
below IMAX, indicating that Q1’s drain current has ex-
ceeded the maximum level, CC starts to pull current out of
the external soft-start capacitor, cutting the duty cycle and
controlling the output current level. The CC comparator
pulls current out of the SS pin in proportion to the voltage
difference between IFB and IMAX. Under minor overload
conditions, the SS pin will fall gradually, creating a time
delay before current limit takes effect. Very short, mild
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC1753CG.PDF ] | |
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