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PDF LTC1545IG Data sheet ( Hoja de datos )
| Número de pieza | LTC1545IG | |
| Descripción | Software-Selectable Multiprotocol Transceiver | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC1545
Software-Selectable
Multiprotocol Transceiver
FEATURES
s Software-Selectable Transceiver Supports:
RS232, RS449, EIA530, EIA530-A, V.35, V.36, X.21
s TUV/Detecon Inc. Certified NET1 and NET2
Compliant (Test Report No. NET2/071601/98)
s TBR2 Compliant (Test Report No. CTR2/071601/98)
s Software-Selectable Cable Termination Using
the LTC1344A
s Complete DTE or DCE Port with LTC1543, LTC1344A
s Operates from Single 5V Supply with LTC1543
U
APPLICATIO S
s Data Networking
s CSU and DSU
s Data Routers
DESCRIPTIO
The LTC®1545 is a 5-driver/5-receiver multiprotocol trans-
ceiver. The LTC1545 and LTC1543 form the core of a
complete software-selectable DTE or DCE interface port that
supports the RS232, RS449, EIA530, EIA530-A, V.35, V.36
or X.21 protocols. Cable termination may be implemented
using the LTC1344A software-selectable cable termination
chip or by using existing discrete designs.
The LTC1545 runs from a 5V supply and the charge pump on
the LTC1543. The part is available in a 36-lead SSOP surface
mount package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
DTE or DCE Multiprotocol Serial Interface with DB-25 Connector
RL TM RI LL CTS DSR
DCD DTR RTS
RXD RXC
TXC SCTE TXD
LTC1545
D5 D4
R5 R4
R3 R2 R1
D3 D2 D1
LTC1543
R3 R2 R1
D3 D2 D1
LTC1344A
21 25 * 18 13 5 10 8
22 6 23 20 19 4 1 7 16 3 9 17
DB-25 CONNECTOR
12 15 11 24 14 2
*OPTIONAL
1545 TA01
1
1 page  
LTC1545
PIN FUNCTIONS
VCC (Pins 1, 19): Positive Supply for the Transceivers.
4.75V ≤ VCC ≤ 5.25V. Connect a 1µF capacitor to ground.
VDD (Pins 2, 20): Positive Supply Voltage for V.28. Con-
nect to VDD Pin 3 on LTC1543 or 8V supply. Connect a 1µF
capacitor to ground.
D1 (Pin 3): TTL Level Driver 1 Input.
D2 (Pin 4): TTL Level Driver 2 Input.
D3 (Pin 5): TTL Level Driver 3 Input.
R1 (Pin 6): CMOS Level Receiver 1 Output.
R2 (Pin 7): CMOS Level Receiver 2 Output.
R3 (Pin 8): CMOS Level Receiver 3 Output.
D4 (Pin 9): TTL Level Driver 4 Input.
R4 (Pin 10): CMOS Level Receiver 4 Output.
M0 (Pin 11): TTL Level Mode Select Input 0 with Pull-Up
to VCC.
M1 (Pin 12): TTL Level Mode Select Input 1 with Pull-Up
to VCC.
M2 (Pin 13): TTL Level Mode Select Input 2 with Pull-Up
to VCC.
DCE/DTE (Pin 14): TTL Level Mode Select Input with
Pull-Up to VCC. Logic high enables Driver 3. Logic low
enables Receiver 1.
D4ENB (Pin 15): TTL Level Enable Input with Pull-Up to
VCC. Logic low enables Driver 4.
R4EN (Pin 16): TTL Level Enable Input with Pull-Up to VCC.
Logic high enables Receiver 4.
R5 (Pin 17): CMOS Level Receiver 5 Output.
D5 (Pin 18): TTL Level Driver 5 Input.
D5 A (Pin 21): Driver 5 Output.
R5 A (Pin 22): Receiver 5 Input.
R4 A (Pin 23): Receiver 4 Input.
D4 A (Pin 24): Driver 4 Input.
R3 B (Pin 25): Receiver 3 Noninverting Input.
R3 A (Pin 26): Receiver 3 Inverting Input.
R2 B (Pin 27): Receiver 2 Noninverting Input.
R2 A (Pin 28): Receiver 2 Inverting Input.
D3/R1 B (Pin 29): Receiver 1 Noninverting Input and
Driver 3 Noninverting Output.
D3/R1 A (Pin 30): Receiver 1 Inverting Input and Driver 3
Inverting Output.
D2 B (Pin 31): Driver 2 Noninverting Output.
D2 A (Pin 32): Driver 2 Inverting Output.
D1 B (Pin 33): Driver 1 Noninverting Output.
D1 A (Pin 34): Driver 1 Inverting Output.
GND (Pin 35): Ground.
VEE (Pin 36): Negative Supply Voltage. Connect to VEE Pin
26 on LTC1543. Connect a 1µF capacitor to ground.
TEST CIRCUITS
A
VOD
B
RL
RL VOC
1545 F01
Figure 1. V.11 Driver Test Circuit
B RL
A 100Ω
CL
100pF
CL
100pF
B
A
R
15pF
1545 F02
Figure 2. V.11 Driver/Receiver AC Test Circuit
5
5 Page 
LTC1545
APPLICATIONS INFORMATION
GENERATOR
BALANCED
INTERCONNECTING
CABLE
LOAD
CABLE
TERMINATION
RECEIVER
A A'
C C'
Figure 16. Typical V.28 Interface
1545 F16
A'
A
R1 LTC1344A
51.5Ω
R5
R8 20k
6k
S1
R3
S2 124Ω
S3
R2
51.5Ω
B'
C'
R4
B 20k
GND
LTC1543
LTC1545
R6
10k
RECEIVER
R7
10k
1545 F17
Figure 17. V.28 Receiver Configuration
GENERATOR
BALANCED
INTERCONNECTING
CABLE
LOAD
CABLE
TERMINATION
RECEIVER
A A'
50Ω
125Ω
50Ω
125Ω
50Ω
B
C
50Ω
B'
C'
Figure 18. Typical V.35 Interface
1545 F18
V.35 Interface
A typical V.35 balanced interface is shown in Figure 18. A
V.35 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.35 interface requires a T or delta network termination at
the receiver end and the generator end. The receiver
differential impedance measured at the connector must be
100Ω␣ ±10Ω, and the impedance between shorted termi-
nals (A' and B') and ground C' must be 150Ω ±15Ω.
In V.35 mode, both switches S1 and S2 inside the LTC1344A
are on, connecting the T network impedance as shown in
Figure 19. Both switches in the LTC1543 are off. The 30k
input impedance of the receiver is placed in parallel with
the T network termination, but does not affect the overall
input impedance significantly.
The generator differential impedance must be 50Ω to
150Ω and the impedance between shorted terminals (A
and B) and ground C must be 150Ω ±15Ω. For the
generator termination, switches S1 and S2 are both on and
the top side of the center resistor is brought out to a pin so
it can be bypassed with an external capacitor to reduce
common mode noise as shown in Figure 20.
A'
A
R1 LTC1344A
51.5Ω
R5
R8 20k
6k
S1 R3
S2 124Ω
S3
R2
51.5Ω
B'
C'
R4
B 20k
GND
LTC1543
R6 RECEIVER
10k
R7
10k
1545 F19
Figure 19. V.35 Receiver Configuration
A
LTC1344A
V.35 DRIVER
124Ω
51.5Ω
S1
S2 ON
ON
C1
100pF
51.5Ω
B
C
1545 F20
Figure 20. V.35 Driver Using the LTC1344A
11
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| PDF Descargar | [ Datasheet LTC1545IG.PDF ] | |
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