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PDF LTC1485C Data sheet ( Hoja de datos )

Número de pieza LTC1485C
Descripción Differential Bus Transceiver
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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LTC1485
Differential Bus Transceiver
FEATURES
s ESD Protection over ±10kV
s Low Power: ICC = 1.8mA Typ
s 28ns Typical Driver Propagation Delays with
4ns Skew
s Designed for RS485 or RS422 Applications
s Single 5V Supply
s – 7V to 12V Bus Common-Mode Range Permits ±7V
Ground Difference Between Devices on the Bus
s Thermal Shutdown Protection
s Power-Up/Down Glitch-Free Driver Outputs
s Driver Maintains High Impedance in Three-State or
with the Power Off
s Combined Impedance of a Driver Output and
Receiver Allows up to 32 Transceivers on the Bus
s 60mV Typical Input Hysteresis
s Pin Compatible with the SN75176A, DS75176A, and
SN75LBC176
APPLICATI S
s Low Power RS485/RS422 Transceiver
s Level Translator
DESCRIPTIO
The LTC ®1485 is a low power differential bus/line trans-
ceiver designed for multipoint data transmission standard
RS485 applications with extended common-mode range
(12V to – 7V). It also meets the requirements of RS422.
The CMOS with Schottky design offers significant power
savings over its bipolar counterpart without sacrificing
ruggedness against overload or ESD damage.
The driver and receiver feature three-state outputs, with
the driver outputs maintaining high impedance over the
entire common-mode range. Excessive power dissipation
caused by bus contention or faults is prevented by a
thermal shutdown circuit which forces the driver outputs
into a high impedance state. I/O pins are protected against
multiple ESD strikes of over ±10kV.
The receiver has a fail-safe feature which guarantees a
high output state when the inputs are left open.
Both AC and DC specifications are guaranteed from – 40°C
to 85°C and 4.75V to 5.25V supply voltage range.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATI
DI 4
RO 1
DE
3
DRIVER
5V
8
LTC1485
6
5V
8
LTC1485
6
120
120
7 4000 FT 24 GAUGE TWISTED PAIR 7
DE
3
DRIVER
RECEIVER
RECEIVER
4
DI
1 RO
25
RE
52
RE 1485 TA01
1

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LTC1485C pdf
LTC1485
PI FU CTIO S
RO (Pin 1): Receiver Output. If the receiver output is
enabled (RE low), then if A > B by 200mV, RO will be high.
If A < B by 200mV, then RO will be low.
RE (Pin 2): Receiver Output Enable. A low enables the
receiver output, RO. A high input forces the receiver
output into a high impedance state.
DE (Pin 3): Driver Output Enable. A high on DE enables the
driver outputs, A and B. A low input will force the driver
outputs into a high impedance state.
DI (Pin 4): Driver Input. If the driver outputs are enabled
(DE high), then a low on DI forces the driver outputs A low
and B high. A high on DI will force A high and B low.
GND (Pin 5): Ground Connection.
A (Pin 6): Driver Output/Receiver Input.
B (Pin 7): Driver Output/Receiver Input.
VCC (Pin 8): Positive Supply. 4.75V VCC 5.25V.
TEST CIRCUITS
A
VOD2
B
R
R
VOC
1485 F01
Figure 1. Driver DC Test Load
A
DI DRIVER
B
RDIFF
CL1 A
RECEIVER
CL2 B
RO
15pF
1485 F02
Figure 2. Driver/Receiver Timing Test Circuit
RECEIVER
OUTPUT
S1 1k
VCC
CL 1k
S2
1485 F03
Figure 3. Receiver Timing Test Load
OUTPUT
UNDER TEST
500
CL
S1
VCC
S2
1485 F04
Figure 4. Driver Timing Test Load
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LTC1485C arduino
U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.
LTC1485
N8 Package
8-Lead Plastic DIP
0.400*
(10.160)
MAX
87 65
0.255 ± 0.015*
(6.477 ± 0.381)
12
34
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.009 – 0.015
(0.229 – 0.381)
0.065
(1.651)
TYP
+0.025
0.325 –0.015
( )8.255
+0.635
–0.381
0.045 ± 0.015
(1.143 ± 0.381)
0.100 ± 0.010
(2.540 ± 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.015
(0.380)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
N8 0694
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
11

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