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PDF PIC16C773 Data sheet ( Hoja de datos )
| Número de pieza | PIC16C773 | |
| Descripción | 28/40-Pin/ 8-Bit CMOS Microcontrollers w/ 12-Bit A/D | |
| Fabricantes | Microchip Technology | |
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PIC16C77X
28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 4K x 14 words of Program Memory,
256 x 8 bytes of Data Memory (RAM)
• Interrupt capability (up to 14 internal/external
interrupt sources)
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• In-Circuit Serial Programming™ (ISCP)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
* Enhanced features
Pin Diagram
600 mil. PDIP, Windowed CERDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RA4/T0CKI
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
AVDD
AVSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 RB7
39 RB6
38 RB5
37 RB4
36 RB3/AN9/LVDIN
35 RB2/AN8
34 RB1/SS
33 RB0/INT
32 VDD
31 VSS
30 RD7/PSP7
29 RD6/PSP6
28 RD5/PSP5
27 RD4/PSP4
26 RC7/RX/DT
25 RC6/TX/CK
24 RC5/SDO
23 RC4/SDI/SDA
22 RD3/PSP3
21 RD2/PSP2
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM max. resolution is 10-bit
* • 12-bit multi-channel Analog-to-Digital converter
* • On-chip absolute bandgap voltage reference
generator
* • Synchronous Serial Port (SSP) with SPI™ (Master
Mode) and I2C™
* • Universal Synchronous Asynchronous Receiver
Transmitter, supports high/low speeds and 9-bit
address mode (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls
* • Programmable Brown-out detection circuitry for
Brown-out Reset (BOR)
* • Programmable Low-voltage detection circuitry
This is an advanced copy of the data sheet and therefore the contents and
specifications are subject to change based on device characterization.
© 1999 Microchip Technology Inc.
Advance Information
DS30275A-page 1
1 page  
PIC16C77X
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple-
mentary document to this data sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
FIGURE 1-1: PIC16C773 BLOCK DIAGRAM
There a two devices (PIC16C773 and PIC16C774)
covered by this datasheet. The PIC16C773 devices
come in 28-pin packages and the PIC16C774 devices
come in 40-pin packages. The 28-pin devices do not
have a Parallel Slave Port implemented.
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2, respectively.
EPROM
Program
Memory
4K x 14
Program
Bus
14
Instruction reg
13
Program Counter
Data Bus
8
8 Level Stack
(13-bit)
RAM
File
Registers
256 x 8
RAM Addr (1)
9
Addr MUX
Direct Addr 7
Indirect
8 Addr
FSR reg
PORTA
PORTB
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
RA4/T0CKI
RB0/INT
RB1/SS
RB2/AN8
RB3/AN9/LVDIN
RB7:RB4
OSC1/CLKIN
OSC2/CLKOUT
Instruction
Decode &
Control
Timing
Generation
Low-voltage
Detect
Precision
Reference
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
STATUS reg
3 MUX
ALU
8
W reg
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
12-bit
ADC
MCLR VDD, VSS
AVDD
AVSS
Timer0
Timer1
Timer2
CCP1,2
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
© 1999 Microchip Technology Inc.
Advance Information
DS30275A-page 5
5 Page 
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these
PICmicro® microcontrollers. Each block (Pro-
gram Memory and Data Memory) has its own bus
so that concurrent access can occur.
Additional information on device memory may be found
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
2.1 Program Memory Organization
The PIC16C77X PICmicros have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Each device has 4K x 14 words of pro-
gram memory. Accessing a location above the physi-
cally implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
PIC16C77X
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RP1 RP0 (STATUS<6:5>)
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR.
On-chip
Program
Memory
Interrupt Vector
Page 0
Page 1
0004h
0005h
07FFh
0800h
0FFFh
1000h
3FFFh
© 1999 Microchip Technology Inc.
Advance Information
DS30275A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PIC16C773.PDF ] | |
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