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PDF AM79C982 Data sheet ( Hoja de datos )
| Número de pieza | AM79C982 | |
| Descripción | basic Integrated Multiport Repeater (bIMR) | |
| Fabricantes | Advanced Micro Devices | |
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PRELIMINARY
Am79C982
basic Integrated Multiport Repeater (bIMR)
DISTINCTIVE CHARACTERISTICS
s Fully backward-compatible with existing
IMR/IMR+ device non-managed hub designs
— Pin/socket-compatible with the Am79C980
(IMR) and Am79C981 (IMR+) devices
s Repeater functions comply with IEEE 802.3
Repeater Unit specifications
s Four and eight 10BASE-T port options available
s Low-cost, flexible solutions suitable for
non-managed repeater designs
s Integral 10BASE-T transceivers utilize the
required predistortion transmission technique
s Attachment unit interface (AUI) port allows
connectivity with 10BASE-5 (Ethernet) and
10BASE-2 (Cheapernet) networks, as well as
10BASE-F and/or Fiber Optic Inter-Repeater
Link (FOIRL) segments
s Minimum mode facilitates LED implementation
and provides four LED display options for port
status
s Built-in pulse stretching for carrier sense LED
display
s On-board PLL, Manchester encoder/decoder,
LED display and FIFO
s Expandable to increase number of repeater
ports
s All ports can be separately isolated (partitioned)
in response to excessive collision conditions or
fault conditions
s Network management and optional features are
accessible through a dedicated serial
management port
s Twisted-pair Link Test capability conforming to
the 10BASE-T standard. The receive Link Test
function can be optionally disabled through the
management port to facilitate interoperability
with devices that do not implement the Link Test
function
s Programmable option of Automatic Polarity
Detection and Correction permits automatic
recovery due to wiring errors
s Full amplitude and timing regeneration for
retransmitted waveforms
s Preamble loss effects eliminated by deep FIFO
s CMOS device features high integration and low
power with a single +5 V supply
GENERAL DESCRIPTION
The basic Integrated Multiport Repeater (bIMR™) chip
is a VLSI circuit that provides a system-level solution to
designing a compliant 802.3 repeater incorporating
10BASE-T transceivers. The device integrates the
Repeater functions specified by Section 9 of the
IEEE 802.3 standard and twisted-pair Transceiver
functions complying to the 10BASE-T standard. The
Am79C982-4 provides four and the Am79C982-8 pro-
vides eight integral twisted-pair medium attachment
units (MAUs), and an attachment unit interface (AUI)
port in an 84-pin plastic leaded chip carrier (PLCC).
A network based on the 10BASE-T standard uses un-
shielded twisted-pair cables, therefore providing an
economical solution to networking by allowing the use
of low-cost unshielded twisted-pair (UTP) cable or
existing telephone wiring.
The total number of ports per repeater unit can be in-
creased by connecting multiple bIMR devices through
their expansion ports, hence minimizing the total cost
per repeater port. Furthermore, a general-purpose
attachment unit interface (AUI) provides connection
capability to 10BASE-5 (Ethernet) and 10BASE-2
(Cheapernet) coaxial networks, as well as 10BASE-F
and/or Fiber Optic Inter-Repeater Link (FOIRL) fiber
segments. Network management and test functions
are provided through TTL-compatible I/O pins.
The device is fabricated in CMOS technology and
requires a single +5 V supply.
Publication# 19406 Rev: B Amendment/0
Issue Date: January 1999
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
1-3
1 page  
LOGIC SYMBOL
AUI
Management
Port
LOGIC DIAGRAM
PRELIMINARY
DVDD
DO+
DO–
DI+
DI–
CI+
CI–
AVDD
TXD+
TXP+
TXD–
TXP–
RXD+
RXD–
SCLK Am79C982 DAT
SI JAM
SO
ACK
COL
X2 REQ
X1
TEST
CRS
RST
STR
DVSS
AVSS
AMD
Twisted Pair
Ports
(4 or 8 Ports)
Expansion
Port
Port
Activity
Monitor
19406B-4
Management
Port
AUI
Repeater
State
Machine
Expansion
Port
Twisted Pair
Port 0
Twisted Pair
Port n
(Note)
Note: n=3 for Am79C982-4 and n=7 for Am79C982-8.
Am79C982
19406B-5
1–7
5 Page 
PRELIMINARY
AMD
that port’s transmitter has been inactive for more than 8
to 17 ms. Conversely, if a TP port does not receive any
data packets or Link Test pulses for more than 65 to
132 ms and the Link Test function is enabled for that
port then that port will enter link fail state. A port in link
fail state will be disabled by the bIMR chip (repeater
transmit and receive functions disabled) until it receives
either four consecutive Link Test pulses or a data pack-
et. The Link Test receive function itself can be disabled
via the bIMR chip management port on a port-by-port
basis to allow the bIMR device to interoperate with
pre-10BASE-T twisted pair networks that do not imple-
ment the Link Test function. This interoperability is pos-
sible because the bIMR device will not allow the TP port
to enter link fail state, even if no Link Test pulses or data
packets are being received. Note however that the bIMR
chip will always transmit Link Test pulses to all TP ports
regardless of whether or not the port is enabled, parti-
tioned, in link fail state, or has its Link Test receive func-
tion disabled.
Polarity Reversal
The TP ports have the optional (programmable) ability
to invert (correct) the polarity of the received data if the
TP port senses that the received data packet waveform
polarity is reversed due to a wiring error. This receive
circuitry polarity correction allows subsequent packets
to be repeated with correct polarity. This function is exe-
cuted once following reset or link fail, and has a pro-
grammable enable/disable option on a port-by-port
basis. This function is disabled upon reset and can be
enabled via the bIMR chip Management Port.
Reset
The bIMR device enters reset state when the RST pin is
driven LOW. After the initial application of power, the
RST pin must be held LOW for a minimum of 150 µs
(3000 X1 clock cycles). If the RST pin is subsequently
asserted while power is maintained to the bIMR device,
a reset duration of only 4 µs is required. The bIMR chip
continues to be in the reset state for 10 X1 clocks
(0.5 µs) following the rising edge of RST. During reset,
the output signals are placed in their inactive states.
This means that all analog signals are placed in their idle
states, bidirectional signals are not driven, active LOW
signals are driven HIGH, and all active HIGH signals
and the STR pin are driven LOW.
An internal circuit ensures that a minimum reset pulse is
generated for all internal circuits. For a RST input with a
slow rising edge, the input buffer threshold may be
crossed several times due to ripple on the input
waveform.
In a multiple bIMR chip repeater the RST signal should
be applied simultaneously to all bIMR devices and
should be synchronized to the external X1 clock. Reset
synchronization is also required when accessing the
PAM (Port Activity Monitor).
The SI signal should be held HIGH for at least 500 ns fol-
lowing the rising edge of RST.
Table 1 summarizes the state of the bIMR chip following
reset.
Table 1. bIMR Chip After Reset
Function
Active LOW outputs
Active HIGH outputs
SO Output
DAT, JAM
STR
Transmitters (TP and AUI)
Receivers (TP and AUI)
AUI Partitioning/Reconnection Algorithm
TP Port Partitioning/Reconnection Algorithm
Link Test Function for TP Ports
Automatic Receiver Polarity Reversal Function
State After Reset
HIGH
LOW
HIGH
HI-IMPEDANCE
LOW
IDLE
ENABLED
STANDARD ALGORITHM
STANDARD ALGORITHM
ENABLED, TP PORTS IN LINK FAIL
DISABLED
Pull Up/Pull Down
No
No
No
Either
No
No
Terminated
N/A
N/A
N/A
N/A
Am79C982
1–13
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| PDF Descargar | [ Datasheet AM79C982.PDF ] | |
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