PDF AM79C970 Data sheet ( Hoja de datos )

Número de pieza	AM79C970
Descripción	PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
Fabricantes	Advanced Micro Devices
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PRELIMINARY Am79C970 Advanced Micro PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus Devices DISTINCTIVE CHARACTERISTICS s Single-chip Ethernet controller for the Periph- eral Component Interconnect (PCI) local bus s Supports ISO 8802-3 (IEEE/ANSI 802.3) and Ethernet Standards s Direct interface to the PCI local bus s Compliant to PCI local bus specification (Revision 2.0) s Software compatible with AMD’s Am7990 LANCE, Am79C90 C-LANCE, Am79C960 PCnet-ISA, Am79C961 PCnet-ISA+, Am79C965 PCnet-32, and Am79C900 ILACCTM register and descriptor architecture s Compatible with Am2100/Am1500T and Novell® NE2100/NE1500 driver software s High-performance Bus Master architecture with integrated DMA Buffer Management Unit for low CPU and bus utilization s Big endian byte alignment supported s Single +5 V power supply operation s Low-power, CMOS design with sleep modes allows reduced power consumption for critical battery powered applications and Green PCs s MicrowireTM EEPROM interface supports jumperless design s Individual 136-byte transmit and 128-byte receive FIFOs provide frame buffering for increased system latency, and support the following features: — Automatic retransmission with no FIFO reload — Automatic receive stripping and transmit padding (individually programmable) — Automatic runt packet rejection — Automatic deletion of received collision frames s Look-Ahead Packet Processing (LAPP) concept allows protocol analysis to begin before end of receive frame s Integrated Manchester Encoder/Decoder s Provides integrated Attachment Unit Interface (AUI) and 10BASE-T transceiver with automatic port selection s Automatic Twisted-Pair receive polarity detec- tion and automatic correction of the receive polarity s Optional byte padding to long-word boundary on receive s Dynamic transmit FCS generation programma- ble on a frame-by-frame basis s Internal/external loopback capabilities s Supports the following types of network interfaces: — AUI to external 10BASE2, 10BASE5,10BASE-T or 10BASE-F MAU — Internal 10BASE-T transceiver with Smart Squelch to Twisted-Pair medium s NAND Tree test mode for connectivity testing on printed circuit boards s 132-pin PQFP package GENERAL DESCRIPTION The PCnet-PCI single-chip 32-bit Ethernet controller is a highly integrated Ethernet system solution designed to address high-performance system application require- ments. It is a flexible bus-mastering device that can be used in any application, including network-ready PCs, printers, fax modems, and bridge/router designs. The bus-master architecture provides high data throughput in the system and low CPU and system bus utilization. The PCnet-PCI controller is fabricated with AMD’s ad- vanced low-power CMOS process to provide low oper- ating and standby current for power sensitive applications. The PCnet-PCI controller is a complete Ethernet node integrated into a single VLSI device. It contains a bus in- terface unit, a DMA buffer management unit, an IEEE 802.3-defined Media Access Control (MAC) function, in- dividual 136-byte transmit and 128-byte receive FIFOs, an IEEE 802.3-defined Attachment Unit Interface (AUI) and Twisted-Pair Transceiver Media Attachment Unit (10BASE-T MAU), and a Microwire EEPROM interface. The PCnet-PCI controller is also register compatible with the LANCE (Am7990) Ethernet controller, the C-LANCE (Am79C90) Ethernet controller, the ILACC (Am79C900) Ethernet controller, and all Ethernet 1-868 This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 18220 Rev. C Amendment /0 Issue Date: June 1994 1 page AMD PRELIMINARY USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-947 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-948 Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-948 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-948 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-949 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-949 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-951 Programming Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-951 Sub-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-951 Base-Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-951 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-951 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-951 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-951 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-952 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-952 RAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-952 RAP: Register Address Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-952 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-952 CSR0: PCnet-PCI Controller Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-952 CSR1: IADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-955 CSR2: IADR[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-955 CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-955 CSR4: Test and Features Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-957 CSR6: RX/TX Descriptor Table Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-959 CSR8: Logical Address Filter, LADRF[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-960 CSR9: Logical Address Filter, LADRF[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-960 CSR10: Logical Address Filter, LADRF[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-960 CSR11: Logical Address Filter, LADRF[63:48] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-960 CSR12: Physical Address Register, PADR[15:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-960 CSR13: Physical Address Register, PADR[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-960 CSR14: Physical Address Register, PADR[47:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-961 CSR15: Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-961 CSR16: Initialization Block Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-963 CSR17: Initialization Block Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-963 CSR18: Current Receive Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-963 CSR19: Current Receive Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-963 CSR20: Current Transmit Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-963 CSR21: Current Transmit Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-963 CSR22: Next Receive Buffer Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-963 CSR23: Next Receive Buffer Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-963 CSR24: Base Address of Receive Ring Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-964 CSR25: Base Address of Receive Ring Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-964 CSR26: Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-964 CSR27: Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-964 CSR28: Current Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . 1-964 CSR29: Current Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . 1-964 CSR30: Base Address of Transmit Ring Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-964 CSR31: Base Address of Transmit Ring Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-964 CSR32: Next Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-965 CSR33: Next Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-965 CSR34: Current Transmit Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . 1-965 CSR35: Current Transmit Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . 1-965 CSR36: Next Receive Descriptor Address Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-965 CSR37: Next Receive Descriptor Address Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-965 1-872 Am79C970 5 Page AMD PRELIMINARY ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C970 KC \W ALTERNATE PACKAGING OPTION \W = Trimmed and Formed in a Tray OPTIONAL PROCESSING Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0°C to +70°C) PACKAGE TYPE (per Prod. Nomenclature) K = Plastic Quad Flat Pack (PQB132) SPEED OPTION Not Applicable DEVICE NUMBER/DESCRIPTION Am79C970 PCnet-PCI Single-Chip Ethernet Controller for PCI Local Bus Valid Combinations AM79C970 KC, KC\W Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 1-878 Am79C970 11 Page

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