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PDF AM79C961A Data sheet ( Hoja de datos )
| Número de pieza | AM79C961A | |
| Descripción | PCnet -ISA II Jumperless/ Full Duplex Single-Chip Ethernet Controller for ISA | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AM79C961A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PRELIMINARY
Am79C961A
PCnet™-ISA II Jumperless, Full Duplex Single-Chip
Ethernet Controller for ISA
DISTINCTIVE CHARACTERISTICS
s Single-chip Ethernet controller for the Industry
Standard Architecture (ISA) and Extended
Industry Standard Architecture (EISA) buses
s Supports IEEE 802.3/ANSI 8802-3 and Ethernet
standards
s Supports full duplex operation on the
10BASE-T, AUI, and GPSI ports
s Direct interface to the ISA or EISA bus
s Pin compatible to Am79C961 PCnet-ISA+
Jumperless Single-Chip Ethernet Controller
s Software compatible with AMD’s Am7990
LANCE register and descriptor architecture
s Low power, CMOS design with sleep mode
allows reduced power consumption for critical
battery powered applications
s Individual 136-byte transmit and 128-byte
receive FIFOs provide packet buffering for
increased system latency, and support the
following features:
— Automatic retransmission with no FIFO
reload
— Automatic receive stripping and transmit
padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of received collision
frames
s Dynamic transmit FCS generation
programmable on a frame-by-frame basis
s Single +5 V power supply
s Internal/external loopback capabilities
s Supports 8K, 16K, 32K, and 64K Boot PROMs or
Flash for diskless node applications
s Supports Microsoft’s Plug and Play System
configuration for jumperless designs
s Supports staggered AT bus drive for reduced
noise and ground bounce
s Supports 8 interrupts on chip
s Look Ahead Packet Processing (LAPP)
allows protocol analysis to begin before
end of receive frame
s Supports 4 DMA channels on chip
s Supports 16 I/O locations
s Supports 16 boot PROM locations
s Provides integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with 2 modes of
port selection:
— Automatic selection of AUI or 10BASE-T
— Software selection of AUI or 10BASE-T
s Automatic Twisted Pair receive polarity
detection and automatic correction of the
receive polarity
s Supports bus-master, programmed I/O, and
shared-memory architectures to fit in any PC
application
s Supports edge and level-sensitive interrupts
s DMA Buffer Management Unit for reduced CPU
intervention which allows higher throughput by
by-passing the platform DMA
s JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board level production test
s Integrated Manchester Encoder/Decoder
s Supports the following types of network
interfaces:
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted Pair medium
s Supports LANCE General Purpose Serial
Interface (GPSI)
s 132-pin PQFP package
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 19364 Rev: A Amendment/+3
Issue Date: September 1996
1 page  
PRELIMINARY
FLASH PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
OPTIONAL IEEE ADDRESS PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
EISA CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
BUS INTERFACE UNIT (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
DMA TRANSFERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
1. INITIALIZATION BLOCK DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
2. DESCRIPTOR DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3. FIFO DMA TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
BUFFER MANAGEMENT UNIT (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
REINITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
BUFFER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
DESCRIPTOR RINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
DESCRIPTOR RINGS ACCESS MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
POLLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
TRANSMIT DESCRIPTOR TABLE ENTRY (TDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
RECEIVE DESCRIPTOR TABLE ENTRY (RDTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
MEDIA ACCESS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
TRANSMIT AND RECEIVE MESSAGE DATA ENCAPSULATION. . . . . . . . . . . . . . . . . . . . . . . .61
MANCHESTER ENCODER/DECODER (MENDEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
EXTERNAL CRYSTAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
EXTERNAL CLOCK DRIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
MENDEC TRANSMIT PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
TRANSMITTER TIMING AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
RECEIVE PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
INPUT SIGNAL CONDITIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
CLOCK ACQUISITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
PLL TRACKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
CARRIER TRACKING AND END OF MESSAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
DATA DECODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
DIFFERENTIAL INPUT TERMINATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
COLLISION DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
JITTER TOLERANCE DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
ATTACHMENT UNIT INTERFACE (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
TWISTED PAIR TRANSCEIVER (T-MAU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
TWISTED PAIR TRANSMIT FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
TWISTED PAIR RECEIVE FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
LINK TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
POLARITY DETECTION AND REVERSAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
TWISTED PAIR INTERFACE STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
COLLISION DETECT FUNCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
SIGNAL QUALITY ERROR (SQE) TEST (HEARTBEAT) FUNCTION . . . . . . . . . . . . . . . . . . . . .69
JABBER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
FULL DUPLEX OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
EADI (EXTERNAL ADDRESS DETECTION INTERFACE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
GPSI (GENERAL PURPOSE SERIAL INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
IEEE 1149.1 TEST ACCESS PORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
BOUNDARY SCAN CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
SUPPORTED INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
INSTRUCTION REGISTER AND DECODING LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
BOUNDARY SCAN REGISTER (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
OTHER DATA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
POWER SAVING MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
ACCESS OPERATIONS (SOFTWARE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Am79C961A
5
5 Page 
PRELIMINARY
CONNECTION DIAGRAMS: BUS MASTER MODE
DVSS3
MASTER
DRQ7
DRQ6
DRQ5
DVSS10
DACK7
DACK6
DACK5
LA17
LA18
LA19
LA20
DVSS4
LA21
LA22
LA23
SBHE
DVDD3
SA0
SA1
SA2
DVSS5
SA3
SA4
SA5
SA6
SA7
SA8
SA9
DVSS6
SA10
SA11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Top Side View
Am79C961A
99 XTAL2
98 AVSS2
97 XTAL1
96 AVDD3
95 TXD+
94 TXPD+
93 TXD–
92 TXPD–
91 AVDD4
90 RXD+
89 RXD–
88 DVSS13
87 SD15
86 SD7
85 SD14
84 SD6
83 DVSS9
82 SD13
81 SD5
80 SD12
79 SD4
78 DVDD7
77 SD11
76 SD3
75 SD10
74 SD2
73 DVSS8
72 SD9
71 SD1
70 SD8
69 SD0
68 SLEEP
67 DVDD6
19364A-2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM79C961A.PDF ] | |
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