PDF AM79C873 Data sheet ( Hoja de datos )

Número de pieza	AM79C873
Descripción	NetPHY -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
Fabricantes	Advanced Micro Devices
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PRELIMINARY Am79C873 NetPHY™ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support DISTINCTIVE CHARACTERISTICS s 100BASE-FX direct interface to industry standard electrical/optical transceivers s 10/100BASE-TX physical-layer, single-chip transceiver s Compliant with the IEEE 802.3u 100BASE-TX standard s Compliant with the ANSI X3T12 TP-PMD 1995 standard s Compliant with the IEEE 802.3u Auto- Negotiation protocol for automatic link type selection s Supports the MII with serial management interface s Supports Full Duplex operation for 10 Mbps and 100 Mbps s High performance 100 Mbps clock generator and data recovery circuitry s Adaptive equalization circuitry for 100 Mbps receiver s Controlled output edge rates in 100 Mbps s Supports a 10BASE-T interface without the need for an external ﬁlter s Provides Loopback mode for system diagnostics s Includes ﬂexible LED conﬁguration capability s Digital clock recovery circuit using advanced digital algorithm to reduce jitter s Low-power, high-performance CMOS process s Available in a 100-pin PQFP package GENERAL DESCRIPTION The NetPHY-1 device is a physical-layer, single-chip, low-power transceiver for 100BASE-TX, 100BASE-FX, and 10BASE-T operations. On the media side, it pro- vides a direct interface to Fiber Media for 100BASE-FX Fast Ethernet, Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the IEEE 802.3u Media Independent Interface (MII), the NetPHY-1 device connects to the Medium Access Control (MAC) layer, ensuring a high interoperability among products from different vendors. The NetPHY-1 device uses a low-power, high-perfor- mance CMOS process. It contains the entire physical layer functions of 100BASE-FX and 100BASE-TX as deﬁned by the IEEE 802.3u standard, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), 100BASE-TX Twisted Pair Physical Medium Dependent (TP-PMD) sublayer, and a 10BASE-T Encoder/Decoder (ENDEC). The NetPHY-1 device provides strong support for the Auto-Negotiation function utilizing automatic media speed and protocol selection. The NetPHY-1 device incorporates an inter- nal wave-shaping ﬁlter to control rise/fall time, eliminat- ing the need for external ﬁltering on the 10/100 Mbps signals. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 22164 Rev: A Amendment/+2 Issue Date: February 1999 Refer to AMD’s Website (www.amd.com) for the latest information. 1 page RELATED AMD PRODUCTS PRELIMINARY Part No. Description Controllers Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE™) Integrated Controllers Am79C930 PCnet™-Mobile Single Chip Wireless LAN Media Access Controller Am79C940 Media Access Controller for Ethernet (MACE™) Am79C961A PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus Am79C965A PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses Am79C970A PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus Am79C971 PCnet-FAST Single-Chip Full Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus Am79C972 PCnet-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support Am79C973/ Am79C975 PCnet-Fast III Single-chip 10/100 Mbps PCI Ethernet Controller With Integrated PHY Am79C978 PCnet-Home Single-chip 1/10 Mbps PCI Home networking Controller Physical Layer Devices (Single-Port) Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver Am79761 Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY™-SD) Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Physical Layer Devices (Multi-Port) Am79C871 Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXr™) Am79C988A Quad Integrated Ethernet Transceiver (QuIET™) Am79C989 Quad Ethernet Switching Transceiver (QuEST™) Integrated Repeater/Hub Devices Am79C981 Integrated Multiport Repeater Plus (IMR+) Am79C982 Basic Integrated Multiport Repeater (bIMR) Am79C983 Integrated Multiport Repeater 2 (IMR2™) Am79C984A Enhanced Integrated Multiport Repeater (eIMR™) Am79C985 Enhanced Integrated Multiport Repeater Plus (eIMR+™) Am79C987 Hardware Implemented Management Information Base (HIMIB™) Am79C873 5 5 Page PRELIMINARY Clock Interface OSCI/X1 Crystal or Oscillator Input Input This pin should be connected to a 25 MHz (±50 ppm) crystal if OSC/XTL=0 or a 25 MHz (±50 ppm) external TTL oscillator input, if OSC/XTLB=1. X2 Crystal Oscillator Output Output An external 25 MHz (±50 ppm) crystal should be con- nected to this pin if OSC/XTL=0, or left unconnected if OSC/XTL=1. OSC/XTL Crystal or Oscillator Selector Pin Output OSC/XTL=0: An external 25 MHz (±50ppm) crystal should be connected to X1 and X2 pins. s OSC/XTL=1: An external 25 MHz (±50ppm) oscilla- tor should be connected to X1 and X2 should be left unconnected. CLK25M 25 MHz Clock Output Output/Z This clock is derived directly from the crystal circuit. PHY Address Interface The PHYAD[4:0] pins provide up to 32 unique PHY addresses. An address selection of all zeros (00000) will result in a PHY isolation condition. See the isolate bit description in the BMCR, address 00. PHYAD0 PHY Address 0 Input This pin provides PHY address bit 0 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 8 during power up/reset. PHYAD1 PHY Address 1 Input This pin provides PHY address bit 1 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 7 during power up/reset. PHYAD2 PHY Address 2 Input This pin provides PHY address bit 2 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 6 during power up/reset. PHYAD3 PHY Address 3 Input This pin provides PHY address bit 3 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 5 during power up/reset. PHYAD4 PHY Address 4 Input This pin provides PHY address bit 4 for multiple PHY address applications. The status of this pin is latched into Register 17, bit 4 during power up/reset. Miscellaneous NC No Connect These pins are to be left unconnected (ﬂoating). BGREF Bandgap Voltage Reference Input Connect a 6.01K Ω, 1% resistor between this pin and the BGRET pin to provide an accurate current refer- ence for the NetPHY-1 device. BGRET Bandgap Voltage Reference Return Input This is the return pin for 6.01K Ω resistor connection. TRIDRV Tri-State Digital Output Input When set high, all digital output pins are set to a high impedance state, and I/O pins, go to input mode. RESET Reset Input This pin is the active low input that initializes the NetPHY- 1 device. It should remain low for 30 ms after VCC has stabilized at 5 Vdc (nominal) before it transitions high. TESTMODE Test Mode Control Pin TESTMODE=0: Normal operating mode. Input TESTMODE=1: Enable test mode. Power and Ground Pins The power (VCC) and ground (GND) pins of the Net- PHY-1 device are grouped in pairs of two categories - Digital Circuitry Power/Ground Pairs and Analog Cir- cuitry Power/Ground Pair. DGND Digital Logic Ground These pins are the digital supply pairs. Power DVCC Digital Logic Power Supply These pins are the digital supply pairs. Power AGND Analog Circuit Ground Power These pins are the analog circuit supply pairs. AVCC Analog Circuit Power Supply Power These pins are the analog circuit supply pairs. Am79C873 11 11 Page

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