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PDF AN2492FH Data sheet ( Hoja de datos )
| Número de pieza | AN2492FH | |
| Descripción | Luminance and chrominance signal processing circuit for 8 mm video (NTSC) | |
| Fabricantes | Panasonic Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AN2492FH (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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INTEGRATED CIRCUITS
AN246
Transmission lines and terminations with
Philips Advanced Logic families
Author: Mike Magdaluyo
February 1998
Philips
Semiconductors
1 page  
Philips Semiconductors
Transmission lines and terminations
with Philips Logic families
Application Note
AN246
Figure 5. ALVC16244 I-V curves
SH00098
1998 Feb 05
Figure 6. ALVT16244 I-V curves
5
SH00099
5 Page 
Philips Semiconductors
Transmission lines and terminations
with Philips Logic families
Application Note
AN246
Figure 16 shows another method of series termination.
RS RS RS RS
ZO ZO ZO
Figure 16. Series stub termination
SH00120
Note that the drivers at the end will be driving RS + ZO. Drivers in
the middle should be strong enough to drive RS + ZO/2. Again,
keep stub lengths short.
End Terminations
End terminated line are recommended for distributed loads, and
several methods can be used such as parallel, AC, and diode clamp
methods. Figure 17 shows two parallel termination schemes.
VCC
ZO RT = ZO
ZO
RT = ZO
Figure 17. Parallel terminations
SH00121
With this method, the termination resistance is matched to the
effective line impedance. The advantage is that this method allows
for incident wave switching. The disadvantages are that you need
an extremely strong driver and it consumes high static power.
To reduce the drive requirements and power dissipation for this
configuration, a more practical parallel Thevenin termination is
shown in Figure 18 can be used.
Driver
VCC
R1 || R2 = ZO’
ZO ZO R1
R2 Receiver C
Receiver A
Receiver B
SH00122
Figure 18. Daisy chain topology with split resistor Thevenin
termination
This method is suitable for ABT, LVT, and ALVT families but not
recommended for low voltage CMOS logic if power dissipation is a
concern. The termination is placed at the end of the line as close to
the receiver as possible.
If this termination technique is used on LVC and ALVC drivers, take
precaution not to connect the pull-up resistor to a 5 volt supply in a
mixed 3 volt/5 volt system. This can cause 5 volt supply current to
flow to the 3 volt supply through the upper PMOS transistor’s
parasitic diode of the driver output during the active high state.
If used on a 3-State bus, avoid biasing the receiver input at its
threshold switching voltage which is about 1.5 V for BiCMOS and
CMOS TTL level inputs. Inputs left floating around the threshold
region can consume excessive current or cause oscillations. You
can use the following formula to determine values for R1 and R2 if
they are not equal:
Eq. 13
R1
+
ZO
VCC
VT
and R2
+
ZO
VCC
VCC *
VT
where VT = termination voltage.
A good termination voltage to choose is 2.5 V for TTL thresholds.
Assuming a 50% duty cycle, the average power dissipation of the
resistors will be:
Eq. 14
P + 0.5
ǒ ǓVOH2 )
2R2
VOL2
)
(VCC
–
VOH)2 ) (VCC
2R1
–
VOL)2
Another method to reduce quiescent power dissipation is AC
termination shown in Figure 19. This method is recommended for
distributed loads or when static power consumption is a concern.
Driver
ZO
R1 = ZO
R1
C1
SH00125
Figure 19. AC termination
1998 Feb 05
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet AN2492FH.PDF ] | |
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