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PDF AT28LV256 Data sheet ( Hoja de datos )
| Número de pieza | AT28LV256 | |
| Descripción | 256K 32K x 8 Low Voltage CMOS E2PROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT28LV256
Features
Fast Read Access Time - 200 ns
•• Automatic Page Write Operation
Internal Address and Data Latches for 64-Bytes
Internal Control Timer
• Fast Write Cycle Times
Page Write Cycle Time: 10 ms Maximum
1 to 64-Byte Page Write Operation
• Low Power Dissipation
15 mA Active Current
20 µA CMOS Standby Current
Hardware and Software Data Protection
• DATA Polling for End of Write Detection
•• High Reliability CMOS Technology
Endurance: 10,000 Cycles
Data Retention: 10 Years
• Single 3.3V ± 5% Supply
JEDEC Approved Byte-Wide Pinout
•• Commercial and Industrial Temperature Ranges
Description
The AT28LV256 is a high-performance Electrically Erasable and Programmable
Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power dissipation of just 54 mW. When the device is
deselected, the CMOS standby current is less than 200 µA.
The AT28LV256 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 64-byte page register to allow
writing of up to 64-bytes simultaneously. During a write cycle, the addresses and 1 to
Pin Configurations
(continued)
Pin Name
A0 - A14
Function
Addresses
PDIP, SOIC
Top View
CE Chip Enable
OE Output Enable
WE Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
256K (32K x 8)
Low Voltage
CMOS
E2PROM
AT28LV256
PLCC
Top View
TSOP
Top View
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
0273E
2-145
1 page  
AC Read Characteristics
Symbol
tACC
tCE (1)
tOE (2)
tDF (3, 4)
tOH
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
Output Hold from OE, CE or
Address, whichever occurred first
AC Read Waveforms (1, 2, 3, 4)
AT28LV256-20
Min Max
200
200
0 80
0 55
0
AT28LV256
AT28LV256-25
Min Max
250
250
0 100
0 60
0
Units
ns
ns
ns
ns
ns
Notes: 1. CE may be delayed up to tACC - tCE after the address
transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling
edge of CE without impact on tCE or by tACC - tOE
after an address change without impact on tACC.
Input Test Waveforms and
Measurement Level
3. tDF is specified from OE or CE whichever occurs first
(CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Output Test Load
tR, tF < 20 ns
Pin Capacitance (f = 1 MHz, T = 25°C) (1)
Typ Max
CIN 4 6
COUT
8 12
Note: 1. This parameter is characterized and is not 100% tested.
Units
pF
pF
Conditions
VIN = 0V
VOUT = 0V
2-149
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet AT28LV256.PDF ] | |
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