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PDF CY62157CV25 Data sheet ( Hoja de datos )
| Número de pieza | CY62157CV25 | |
| Descripción | 512K x 16 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62157CV25/30/33
MoBL™
512K x 16 Static RAM
Features
• High speed
— 55 ns and 70 ns availability
• Voltage range:
— CY62157CV25: 2.2V–2.7V
— CY62157CV30: 2.7V–3.3V
— CY62157CV33: 3.0V–3.6V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = fmax (70 ns speed)
• Low standby power
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62157CV25/30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This is ideal for providing More Battery Life™ (MoBL™)
in portable applications such as cellular telephones. The de-
vices also have an automatic power-down feature that signifi-
cantly reduces power consumption by 80% when addresses
are not toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when dese-
lected (CE1 HIGH or CE2 LOW or both BLE and BHE are
HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE1 HIGH or
CE2 LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE2) HIGH. If Byte Low Enable (BLE) is LOW, then data from
I/O pins (I/O0 through I/O7), is written into the location speci-
fied on the address pins (A0 through A18). If Byte High Enable
(BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is
written into the location specified on the address pins (A0
through A18).
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable
2 (CE2) HIGH while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on I/O0 to
I/O7. If Byte High Enable (BHE) is LOW, then data from mem-
ory will appear on I/O8 to I/O15. See the truth table at the back
of this data sheet for a complete description of read and write
modes.
The CY62157CV25/30/33 are available in a 48-ball FBGA
package.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A 6 512K × 16
A 5 RAM Array
A 4 2048 × 4096
A3
A2
A1
A0
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power-down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE2
CE1
CE2
CE1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05014 Rev. *C
Revised April 23, 2002
1 page  
CY62157CV25/30/33
MoBL™
AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
INCLUDING
JIG AND
SCOPE
R2
VCC Typ
GND
10%
Rise TIme: 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
R1
R2
RTH
VTH
2.5V
16.6
15.4
8.0
1.20
3.0V
1.105
1.550
0.645
1.75
3.3V
1.216
1.374
0.645
1.75
Unit
K Ohms
K Ohms
K Ohms
Volts
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
tCDR[5]
tR[6]
Description
VCC for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Conditions
VCC = 1.5V
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Data Retention Waveform[7]
Min.
1.5
0
tRC
Typ.[4]
4
Max.
Vccmax
20
Unit
V
µA
ns
ns
VCC
CE1 or
BHE.BLE
or
CE2
VCC(min.)
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC(min.)
tR
Note:
6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) >100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05014 Rev. *C
Page 5 of 13
5 Page 
CY62157CV25/30/33
MoBL™
Truth Table
CE1 CE2
HX
XL
XX
LH
LH
WE
X
X
X
H
H
L HH
L HH
L HH
L HH
LHL
LHL
LHL
OE BHE BLE
Inputs/Outputs
Mode
X X X High Z
Deselect/Power-Down
X X X High Z
Deselect/Power-Down
X H H High Z
Deselect/Power-Down
L L L Data Out (I/OO–I/O15) Read
L H L Data Out (I/OO–I/O7); Read
I/O8–I/O15 in High Z
L L H Data Out (I/O8–I/O15); Read
I/O0–I/O7 in High Z
H L L High Z
Output Disabled
H H L High Z
Output Disabled
H L H High Z
Output Disabled
X L L Data In (I/OO–I/O15) Write
X H L Data In (I/OO–I/O7); Write
I/O8–I/O15 in High Z
X L H Data In (I/O8–I/O15); Write
I/O0–I/O7 in High Z
Power
Standby (ISB)
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Document #: 38-05014 Rev. *C
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CY62157CV25.PDF ] | |
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