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PDF CY62147VLL-70ZI Data sheet ( Hoja de datos )
| Número de pieza | CY62147VLL-70ZI | |
| Descripción | 4M (256K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62147V MoBL®
4M (256K x 16) Static RAM
Features
• Wide voltage range: 2.7V–3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package available in a standard 44-pin TSOP Type II
(forward pinout) package
Functional Description[1]
The CY62147V is a high-performance CMOS static RAM
organized as 256K words by 16 bits. These devices feature
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL®) in
portable applications such as cellular telephones. The devices
also have an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH) or when CE is LOW and both BLE and
BHE are HIGH. The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Logic Block Diagram
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
256K x 16
RAM Array
2048 x 2048
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
Power-down
Circuit
CE
BHE
BLE
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05050 Rev. *A
Revised August 28, 2002
1 page  
Switching Waveforms
Read Cycle No. 1[12, 13]
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
Read Cycle No. 2 [13, 14]
CE
tAA
tRC
tRC
OE
BHE/BLE
tACE
tDOE
tLZOE
tDBE
tLZBE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
tLZCE
tPU
50%
[10, 15, 16]
Write Cycle No. 1 (WE Controlled)
ADDRESS
tWC
CY62147V MoBL®
DATA VALID
DATA VALID
tPD
tHZCE
tHZOE
tHZBE
HIGH
IMPEDANCE
50%
ICC
ISB
CE
tAW
tSA
WE
tPWE
tHA
BHE/BLE
OE
DATA I/O
NOTE 17
tHZOE
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05050 Rev. *A
tBW
tSD
DATAIN VALID
tHD
Page 5 of 9
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY62147VLL-70ZI.PDF ] | |
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