PDF CY28RS400 Data sheet ( Hoja de datos )

Número de pieza	CY28RS400
Descripción	Clock Generator for ATI RS400 Chipset
Fabricantes	Cypress Semiconductor
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CY28RS400 Clock Generator for ATI RS400 Chipset Features • Supports Intel CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks • 48-MHz USB clock • 33-MHz PCI clock • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin SSOP and TSSOP packages CPU SRC PCI REF USB_48 x3 x8 x1 x 3 x 1 Block Diagram XIN XOUT CPU_STP# CLKREQ[0:1]# FS_[C:A] VTT_PWRGD# IREF XTAL OSC PLL Ref Freq PLL1 Divider Network PD PLL2 SDATA SCLK I2C Logic Pin Configuration VDD_REF REF[0:2] Xin XOUT VDD_CPU CPUT[0:2], CPUC[0:2], VDD_48 USB_48 VSS_48 VSDRDC_TS[0R:5C],SRCCV[0T:5T] _PWRGDS#C/PLDK VDD_SRCS SDATA SRCST[0:1],SRCSC[0:1] FSC VDD_PCI PCI CLKREQ#0 CLKREQ#1 SRCT5 SRCC5 VDD_SRC VDD_48 MHz VSS_SRC SRCT4 SRCC4 SRCT3 USB_48 SRCC3 VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC SRCST1 SRCSC1 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 56 SSOP/TSSOP VDD_REF VSS_REF REF0/FSA REF1/FSB REF2 VDD_PCI PCI0/409_410 VSS_PCI CPU_STOP# CPUT0 CPUC0 VDD_CPU VSS_CPU CPUT1 CPUC1 CPUT2 CPUC2 VDDA VSSA IREF VSS_SRC1 VDD_SRC1 SRCT0 SRCC0 VDD_SRCS VSS_SRCS SRCST0 SRCSC0 Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07637 Rev. B Revised October 19, 2004 1 page Control Registers Byte 0:Control Register 0 Bit @Pup 71 61 51 41 31 21 11 01 Name SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 SRC[T/C]2 SRC[T/C]1 SRC [T/C]0 SRCS[T/C]1 SRCS[T/C]0 Byte 1: Control Register 1 Bit @Pup 71 61 51 41 31 21 11 01 Name REF2 REF1 REF0 PCI0 USB_48 CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Byte 2: Control Register 2 Bit @Pup 71 61 51 40 31 20 11 Name CPUT/C SRCT/C USB_48 PCI Reserved Reserved CPU SRC Reserved Document #: 38-07637 Rev. B Description SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRCS[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRCS[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description REF2 Output Enable 0 = Disable, 1 = Enable REF1 Output Enable 0 = Disable, 1 = Enable REF0 Output Enable 0 = Disable, 1 = Enable PCI0 Output Enable 0 = Disable, 1 = Enable USB_48MHz Output Enable 0 = Disable, 1 = Enable CPU[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description Spread Spectrum Selection ‘0’ = -0.35% ‘1’ = -0.50% 48MHz Output Drive Strength 0 = 1x, 1 = 2x 33MHz Output Drive Strength 0 = 1x, 1 = 2x Reserved Reserved CPU/SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on Reserved CY28RS400 Page 5 of 19 5 Page CY28RS400 CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) 1.8mS CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) Figure 7. CPU_STP#= Driven, CPU_PD = Driven 1.8mS Figure 8. CPU_STP# = Hi-Z, CPU_PD = Hi-Z CLK_REQ[0:1]# Description The CLKREQ#[1:0] signals are active low input used for clean stopping and starting selected SRC outputs. The outputs controlled by CLKREQ#[1:0] are determined by the settings in register bytes 4 and 5. The CLKREQ# signal is a de-bounced signal in that it’s state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or de-assertion. (The assertion and de-assertion of this signal is absolutely asynchronous). CLK_REQ[0:1]# De-assertion [Low to High transition] The impact of deasserting the CLKREQ#[1:0] pins is all DIF outputs that are set in the control registers to stoppable via de-assertion of CLKREQ#[1:0] are to be stopped after their next transition. When the control register CLKREQ# drive mode bit is programmed to ‘0’, the final state of all stopped SRC signals is SRCT clock = High and SRCC = Low. There is to be no change to the output drive current values, SRCT will be driven high with a current value equal 6 x Iref,. When the control register CLKREQ# drive mode bit is programmed to ‘1’, the final state of all stopped DIF signals is low, both SRCT clock and SRCC clock outputs will not be driven. CLK_REQ[0:1]# Assertion [High to Low transition] All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the assertion to active outputs is between two–six SRC clock periods (two clocks are shown) with all SRC outputs resuming simultaneously. If the CLKREQ# drive mode bit is programmed to ‘1’ (three-state), the all stopped SRC outputs must be driven high within 10 ns of CLKREQ#[1:0] assertion to a voltage greater than 200 mV. CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 9. CLK_REQ#[0:1] Assertion/Deassertion Waveform Document #: 38-07637 Rev. *B Page 11 of 19 11 Page

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