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PDF CY28301 Data sheet ( Hoja de datos )
| Número de pieza | CY28301 | |
| Descripción | Frequency Generator for Intel Integrated Chipset | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY28301
Frequency Generator for Intel® Integrated Chipset
Features
• Single chip FTG solution for Intel® Solano/810E/810
• Support SMBus byte Read/Write and block Read/Write
operations to simplify system BIOS development
• Vendor ID and revision ID support
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Two copies of CPU clock
• Thirteen copies of SDRAM clock
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Three copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• One copy of 14.31818-MHz reference clock
Block Diagram
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ................................................... 500 ps
CPU, 3V66 Output Skew:............................................ 175 ps
SDRAM, APIC, 48-MHz Output Skew: ........................250 ps
PCI Output Skew:........................................................ 500 ps
CPU to SDRAM Skew (@ 133 MHz) ......................... ±0.5 ns
CPU to SDRAM Skew (@ 100 MHz)..................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz) ........................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead)...........................1.5 to 3.5 ns
PCI to APIC Skew ...................................................... ±0.5 ns
Pin Configuration[1]
VDD_REF
X1
X2
SDATA
SCLK
(FS0:4)
XTAL
OSC
PLL REF FREQ
SMBus
Logic
Divider,
Delay, and
Phase
Control
Logic
PLL 1
PD#
PLL2
/2
REF/FS1
VDD_CPU
CPU0:1
2
VDD_APIC
APIC
VDD_3V66
3V66_0:2
3
VDD_PCI
PCI0
PCI1
PCI2/SEL24_48MHz#*
5 PCI3:7
VDD_SDRAM
SDRAM0:11,
13 SDRAM_F
VDD_48MHz
48MHz/FS0
24_48MHz
VDD_REF
X1
X2
GND_REF
GND_3V66
3V66_0
3V66_1
3V66_2
VDD_3V66
VDD_PCI
PCI0
PCI1
PCI2/SEL24_48MHz#*
GND_PCI
PCI3
PCI4
PCI5
VDD_PCI
PCI6
PCI7
GND_PCI
PD#*
SCLK
SDATA
VDD_SDRAM
SDRAM11
SDRAM10
GND_SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 REF/FS1*
55 VDD_APIC
54 APIC
53 VDD_CPU
52 CPU0
51 CPU1
50 GND_CPU
49 GND_SDRAM
48 SDRAM0
47 SDRAM1
46 SDRAM2
45 VDD_SDRAM
44 SDRAM3
43 SDRAM4
42 SDRAM5
41 GND_SDRAM
40 SDRAM6
39 SDRAM7
38 SDRAM_F
37 VDD_SDRAM
36 GND_48MHz
35 24_48MHz
34 48MHz/FS0*
33 VDD_48MHz
32 VDD_SDRAM
31 SDRAM8
30 SDRAM9
29 GND_SDRAM
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. Design
should not rely solely on internal pull-up resistor to set I/O pins HIGH.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07011 Rev. *C
Revised September 24, 2002
1 page  
CY28301
CY28301 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register 0
Bit Pin#
Bit 7
–
Bit 6
–
Bit 5
–
Bit 4
–
Bit 3
–
Bit 2
Bit 1
Bit 0
–
–
–
Name
SEL1
SEL0
Reserved
Reserved
FS_Override
Spread Select2
Spread Select1
Spread Select0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
2. All unused register bits (reserved and N/A) should be
written to a “0” level.
3. All register bits labeled “Initialize to 0" must be written to “0”
during initialization.
Default
0
0
0
0
0
0
0
0
Description
See 5
See 5
Reserved
Reserved
0 = Select operating frequency by FS[1:0] input pins
1 = Select operating frequency by SEL[1:0] settings
‘000’ = Normal (spread off)
‘001’ = Test mode
‘010’ = Reserved
‘011’ = Three-stated
‘100’ = –0.5%
‘101’ = –0.75%
‘110’ = –1.0%
‘111’ = –0.3%
Byte 1: Control Register 1
Bit Pin#
Bit 7
56
Bit 6
34
Bit 5 –
Bit 4 –
Bit 3 –
Bit 2 –
Bit 1 56
Bit 0 56
Name
Latched FS1 input
Latched FS0 input
Reserved
Reserved
Reserved
Reserved
REF
REF_DRV
Default
X
X
0
0
0
0
1
0
Description
Latched FS[1:0] inputs. These bits are Read-only.
Reserved
Reserved
Reserved
Reserved
(Active/Inactive)
REF Clock output drive strength
0 = Normal
1= High drive
Document #: 38-07011 Rev. *C
Page 5 of 15
5 Page 
DC Operating Requirements (continued)
Parameter
Description
VDDQ3 = 3.3V ±5%
Voh3
Vol3
VDDQ3 = 3.3V ±5%
Vpoh3
Vpol3
3.3V Output High Voltage
3.3V Output Low Voltage
PCI Bus Output High Voltage
PCI Bus Output Low Voltage
Condition
Ioh = (–1 mA)
Iol = (1 mA)
Ioh = (–1 mA)
Iol = (1 mA)
Cin
Cxtal
Cout
Lpin
Ta
Input Pin Capacitance
Xtal Pin Capacitance
Output Pin Capacitance
Pin Inductance
Ambient Temperature
No airflow
CY28301
Min.
.4
2.4
13.5
0
0
Max.
0.4
0.55
5
22.5
6
7
70
Unit
V
V
V
V
pF
pF
pF
nH
°C
Document #: 38-07011 Rev. *C
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CY28301.PDF ] | |
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