PDF CY28158 Data sheet ( Hoja de datos )

Número de pieza	CY28158
Descripción	Spread Spectrum Timing Solution for Serverworks Chipset
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY28158 Spread Spectrum Timing Solution for Serverworks Chipset Features • Maximized EMI suppression using Cypress’s spread spectrum technology • Based on Industry Standard CK133 Pinout with all out- puts compliant to CK98 specifications • 0.5% downspread outputs deliver up to 10dB lower EMI • 6 skew-controlled copies of CPU output • 6 copies of PCI output (synchronous w/CPU output) • 2 copies of 66 MHz fixed frequency 3.3V clock • 3 copies of 16.67 MHz IOAPIC clock, synchronous to CPU clock • 1 copy of 48 MHz USB output • 2 copies of 14.31818 MHz reference clock • Programmable to 133 or 100 MHz operation • Power management control pins for clock stop and shut down • Available in 56-pin SSOP Key Specifications Supply Voltages:...................................... VDD33 = 3.3V ± 5% ................................................................ VDD25 = 2.5V ± 5% CPU Output Jitter: ....................................................<150 ps CPU Output Skew: ....................................................<175 ps CPU to 3V66 Output Offset: 0.0 to1.5 ns (CPU leads) CPU to IOAPIC Output Offset 1.5 to 4.0 ns (CPU leads) CPU to PCI Output Offset................. 0 to 4.0 ns (CPU leads) Table 1. Pin Selectable Frequency. SEL133/100# 1 0 CPU0:5 (MHz) 133 100 PCI 33.3 33.3 Block Diagram X1 X2 CPU_STOP# XTAL OSC 2 REF0:1 STOP Clock Logic 6 CPU0:5 SPREAD# SEL0 SEL1 SEL133/100# PWRDWN# PCI_STOP# PLL 1 Power Down Logic ÷2/÷1.5 STOP Clock Logic STOP ÷2 Clock Logic ÷2 2 3V66_0:1 1 PCI_F 5 PCI1:5 3 IOAPIC0:2 Tristate Logic Pin Configuration GND_REF REF0 REF1 VDD_REF X1 X2 GND_PCI GND_PCI PCI_F VDD_PCI PCI1 PCI2 GND_PCI PCI3 PCI4 VDD_PCI VDD_PCI PCI5 GND_PCI GND_3V66 GND_3V66 VDD_3V66 VDD_3V66 GND_3V66 3V66_0 3V66_1 VDD_3V66 SEL133/100# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 VDD_IOAPIC 55 IOAPIC2 54 IOAPIC1 53 IOAPIC0 52 GND_IOAPIC 51 VDD_CPU 50 CPU5 49 CPU4 48 GND_CPU 47 VDD_CPU 46 CPU3 45 CPU2 44 GND_CPU 43 VDD_CPU 42 CPU1 41 CPU0 40 GND_CPU 39 VDDA 38 GNDA 37 PCI_STOP# 36 CPU_STOP# 35 PWR_DWN# 34 SPREAD# 33 SEL1 32 SEL0 31 VDD_48MHZ 30 48MHZ 29 GND_48MHZ PLL2 1 48MHz Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-07039 Rev. B Revised June 25, 2004 1 page CY28158 Electrical Characteristics Over the Operating Range (continued) Parameter Description IDD3 3.3V Power Supply Cur- rent IDDPD2 IDDPD3 2.5V Shutdown Current 3.3V Shutdown Current Test Conditions VDDA/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz VDDA/VDD33 = 3.465V, VDD25 = 2.625V VDDA/VDD33 = 3.465V, VDD25 = 2.625V Min. Max. Unit 160 mA 100 µA 200 µA Switching Characteristics[5] Over the Operating Range Parameter t1 t2 Output All CPU, IOAPIC Description Output Duty Cycle[6] Rising Edge Rate Test Conditions t1A/t1B Between 0.4V and 2.0V Min. 45 1.0 Max. 55 4.0 t2 48MHZ, REF Rising Edge Rate Between 0.4V and 2.4V t2 PCI, 3V66 Rising Edge Rate Between 0.4V and 2.4V t3 CPU, Falling Edge Rate Between 2.0V and 0.4V IOAPIC 0.5 2.0 1.0 4.0 1.0 4.0 t3 48MHZ, REF Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 t3 PCI, 3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 t6 CPU CPU-CPU Skew Measured at 1.25V 175 t8 IOAPIC IOAPIC-IOAPIC Skew Measured at 1.25V 250 t9 3V66 3V66-3V66 Skew Measured at 1.5V 250 t10 PCI PCI-PCI Skew Measured at 1.5V 500 t11 CPU, 3V66 CPU-3V66 Clock Skew CPU leads. Measured at 1.25V for 0 1.5 2.5V clocks and 1.5V for 3.3V clocks t12 3V66, PCI 3V66-PCI Clock Skew 3V66 leads. Measured at 1.5V 0.5 2.5 t13 CPU, IOAPIC CPU-IOAPIC Clock Skew CPU leads. Measured at 1.25V 1.5 4 CPU Cycle-Cycle Clock Jitter With all outputs running 150 IOAPIC Cycle-Cycle Clock Jitter 500 48MHZ Cycle-Cycle Clock Jitter 500 3V66 Cycle-Cycle Clock Jitter 500 REF Cycle-Cycle Clock Jitter 1000 CPU, PCI Settle Time CPU and PCI clock stabilization from power-up 3 Notes: 4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 5. All parameters specified with loaded outputs. 6. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. Unit % V/ns V/ns V/ns V/ns V/ns V/ns ps ps ps ps ns ns ns ps ps ps ps ps ms Document #: 38-07039 Rev. B Page 5 of 10 5 Page

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