PDF CY27EE16ZE Data sheet ( Hoja de datos )

Número de pieza	CY27EE16ZE
Descripción	1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY27EE16ZE 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM Features Benefits • 18 kbits of EEPROM 16 kbits independent scratch 2 kbits dedicated to clocking functions Higher level of integration and reduced component count by combining EEPROM and PLL. Independent EEPROM may be used for scratch memory, or to store up to eight clock configurations • Integrated, phase-locked loop with programmable P High-performance PLL enables control of output frequencies that are and Q counters, output dividers, and optional customizable to support a wide range of applications analog VCXO, digital VCXO, spread spectrum for EMI reduction • In system programmable through I2C Serial Programming Interface (SPI). Both the SRAM and non-volatile EEPROM memory bits are program- mable with the 3.3V supply Familiar industry standard eases programming effort and enables update of data stored in 16K EEPROM scratchpad and 2K EEPROM clock control block while CY27EE16ZE is installed in system • Low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs • VCXO with analog adjust Write Protect (WP pin) can be programmed to serve as an analog control voltage for a VCXO.The VCXO function is still available with a DCXO, or digitally controlled (through SPI) crystal oscillator if the pin is functioning as WP • 3.3V Operation (optional 2.5V outputs) Meets industry-standard voltage platforms • 20-lead Exposed Pad, EP-TSSOP Industry standard packaging saves on board space Part Number CY27EE16ZE Outputs Input Frequency Range Output Frequency Range 6 1 – 167 MHz (Driven Clock Input) {Commercial} 80 kHz – 200 MHz (3.3V) {Commercial} 1 –150 MHz (Driven Clock Input) {Industrial} 80 kHz –167 MHz (3.3V) {Industrial} 8 – 30 MHz (Crystal Reference) {Comm. or Ind.} 80 kHz –167 MHz (2.5V) {Commercial} 80 kHz – 150 MHz (2.5V) {Industrial} Logic Block Diagram XIN XOUT VCX/WP PDM/OE [I2C- SPI:]SCL SDAT OSC QΦ VCO P PLL Clock Configuration 8x2k EEPROM Memory Array VDD VSS VDDL VSSL AVDD AVSS OUTPUT DIVIDERS CLOCK1 Output Crosspoint Switch Array CLOCK2 CLOCK3 CLOCK4 CLOCK5 CLOCK6 Pin Configurations CY27EE16ZE 20-pin EP-TSSOP XIN 1 VDD 2 CLOCK6 3 AVDD 4 SDAT 5 AVSS 6 VSSL 7 CLOCK1 8 CLOCK2 9 OE/PDM 10 20 XOUT 19 VDD 18 CLOCK5 17 VCXO/WP 16 VSS 15 CLOCK4 14 VDDL 13 SCL 12 CLOCK3 11 VDDL Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07440 Rev. B Revised June 30, 2003 1 page DIV1N [OCH] DIV1SRC [OCH] REF Qtotal (Q+2) [42H] PFD VCO Ptotal (2(PB+4)+PO) [40H], [41H], [42H] 1 0 1 0 CY27EE16ZE /DIV1N /2 /3 Divider Bank 1 Divider Bank 2 /4 /2 /DIV2N CLKSRC Crosspoint Switch Matrix [44H] [44H] [44H,45H] [45H] [45H,46h] [46H] CLOCK1 CLOCK2 CLOCK3 CLOCK4 CLOCK5 CLOCK6 DIV2SRC [47H] DIV2N [47H] CLKOE [09H] Figure 2. Basic Block Diagram of CY27EE16ZE PLL Reference Frequency (REF) The reference frequency can be a crystal or a driven frequency. For crystals, the frequency range must be between 8 MHz and 30 MHz. For a driven frequency, the frequency range must be between 1 MHz and 167 MHz (Commercial Temp.) or 150 MHz (Industrial Temp.). Using a Crystal as the Reference Input The input crystal oscillator of the CY27EE16ZE is an important feature because of the flexibility it allows the user in selecting a crystal as a reference frequency source. The input oscillator has programmable gain, allowing for maximum compatibility with a reference crystal, regardless of manufacturer, process, performance and quality. Programmable Crystal Input Oscillator Gain Settings The Input crystal oscillator gain (XDRV) is controlled by two bits in register 12H, and are set according to Table 3. The parameters controlling the gain are the crystal frequency, the internal crystal parasitic resistance (ESR, available from the manufacturer), and the CapLoad setting during crystal start-up. Bits 3 and 4 of register 12H control the input crystal oscillator gain setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The setting is programmed according to Table 3. All other bits in the register are reserved and should be programmed LOW. See Table 4 for bit locations and values. Table 3. Programmable Crystal Input Oscillator Gain Settings Calculated CapLoad Value Crystal ESR Crystal Input Frequency 8 – 15 MHz 15 – 20 MHz 20 – 25 MHz 25 – 30 MHz 00H – 20H 30Ω 60Ω 00 01 01 10 01 10 10 10 20H – 30H 30Ω 60Ω 01 10 01 10 10 10 10 11 30H – 40H 30Ω 60Ω 01 10 10 10 10 11 11 N/A Table 4. Register Map for Input Crystal Oscillator Gain Setting Address 12H D7 FTAAddrSrc(1) default=0 D6 FTAAddrSrc(0) default=0 D5 D4 D3 D2 D1 D0 XCapSrc XDRV(1) XDRV(0) 0 0 0 default=1 Document #: 38-07440 Rev. B Page 5 of 17 5 Page Sequential Read Sequential read operations follow the same process as random reads except that the master issues an acknowledge instead of a STOP condition after transmission of the first 8-bit data word. This action results in an incrementing of the internal address pointer, and subsequently output of the next 8-bit data word. By continuing to issue acknowledges instead of STOP conditions, the master may serially read the entire contents of the 16-kbit EEPROM scratchpad memory. When the internal address pointer points to the FFH word of a EEPROM block, after the next increment, the pointer will point to the 00H word of the next block. After incrementing to the FFH word of the eighth block, the next increment will point the pointer to the 00H word of the 1st EEPROM block. Similarly, sequential reads within either the EEPROM or SRAM clock configuration blocks will wrap within the block to the first word of the same block after reaching the end of either block. SCL CY27EE16ZE SDAT START Condition Address or Acknowledge Valid Data may be changed STOP Condition Figure 3. Data Transfer Sequence on the Serial Bus SDAT Write Multiple Contiguous Registers 1 Bit 1 Bit 1 Bit Slave Slave R/W = 0 ACK ACK 1 Bit Slave ACK 1 Bit Slave ACK 7-bit Device Address 8-bit Register Address (XXH) 8-bit Register Data (XXH) 8-bit Register Data (XXH+1) 8-bit Register Data (XXH+2) Start Signal SDAT Read 1 Bit 1 Bit Slave R/W = 1 ACK 1 Bit Slave ACK Current Address 7-bit Device Address Read Start Signal 8-bit Register Data 1 Bit Master ACK Stop Signal 1 Bit Slave ACK 1 Bit Slave ACK 1 Bit Slave ACK 8-bit Register Data (XXH) 8-bit Register Data (X0H) 16 byte wrap SDAT Read Multiple Contiguous Registers 1 Bit 1 Bit Slave R/W = 0 ACK 1 Bit Slave ACK 1 Bit Master ACK 1 Bit Master ACK 7-bit Device Address 8-bit Register Address (XXH) 7-bit Device Address +R/W=1 8-bit Register Data (XXH) 8-bit Register Data (XXH+1) 1 Bit Master ACK 1 Bit Master ACK 1 Bit Master ACK 8-bit Register Data (8FFH) 8-bit Register Data (000H) Start Signal Repeated Start bit Figure 4. Data Frame Architecture 1 Bit Slave ACK Stop Signal 1 Bit Master ACK Stop Signal Document #: 38-07440 Rev. *B Page 11 of 17 11 Page

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