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PDF CY2280PVC-21S Data sheet ( Hoja de datos )
| Número de pieza | CY2280PVC-21S | |
| Descripción | 100-MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY2280
100-MHz Pentium® II Clock Synthesizer/Driver with
Spread Spectrum for Mobile or Desktop PCs
Features
• Mixed 2.5V and 3.3V operation
• Clock solution for Pentium® II, and other similar pro-
cessor-based motherboards
— Four 2.5V CPU clocks up to 100 MHz
— Eight 3.3V sync. PCI clocks, one free-running
— Two 3.3V 48-MHz USB clocks
— Three 3.3V Ref. clocks at 14.318 MHz
— Two 2.5V APIC clocks at 14.318 MHz or PCI/2
• EMI control
— Spread spectrum clocking
— Factory-EPROM programmable spread spectrum
margin
— Factory-EPROM programmable output drive and
slew rate
• Factory-EPROM programmable CPU clock frequencies
for custom configurations
• Available in space-saving 48-pin SSOP package
Functional Description
The CY2280 is a Spread Spectrum clock synthesizer/driver for
a Pentium II, or other similar processor-based PC requiring
100-MHz support. All of the required system clocks are provid-
ed in a space-saving 48-pin SSOP package. The CY2280 can
be used with the CY231x for a total solution for systems with
SDRAM.
The CY2280 provides the option of spread spectrum clocking
on the CPU and PCI clocks for reduced EMI. A downspread
percentage is introduced when the SEL_SS input is asserted.
The device can be run without spread spectrum when the
SEL_SS input is deasserted. The percentage of spreading is
EPROM-programmable to optimize EMI-reduction.
The CY2280 has power-down, CPU stop, and PCI stop pins
for power management control. The signals are synchronized
on-chip, and ensure glitch-free transitions on the outputs.
When the CPU_STOP input is asserted, the CPU clock out-
puts are driven LOW. When the PCI_STOP input is asserted,
the PCI clock outputs (except the free-running PCI clock) are
driven LOW. When the PWR_DWN pin is asserted, the refer-
ence oscillator and PLLs are shut down, and all outputs are
driven LOW.
CY2280 Selector Guide
Clock Outputs
CPU (66.6, 100 MHz)
PCI (CPU/2, CPU/3)
USB (48 MHz)
APIC (14.318 MHz)
APIC (PCI/2)
Reference (14.318 MHz)
CPU-PCI delay
CPU-APIC delay
Spread Spectrum (Downspread)
–1
4
8
2
2
—
3
1.5−4.0 ns
—
N/A
CY2280 Configuration Options
–11S
4
8
2
2
—
3
1.5−4.0 ns
—
−0.6%
–21S
4
8
2
—
2
3
1.5−4.0 ns
2.0–4.5 ns
−0.6%
Logic Block Diagram
CPU_STOP
XTALIN
XTALOUT
PWR_DWN
SEL0
SEL1
SEL100
SEL_SS
PCI_STOP
14.318
MHz
OSC.
CPU
PLL
Divider
EPROM
Delay
SYS PLL
-1
-2
STOP
LOGIC
STOP
LOGIC
Pentium is a registered trademark of Intel Corporation.
APIC [0:1]
VDDAPIC
REF [0-2]
VDDREF
CPUCLK [0-3]
VDDCPU
PCICLK_F
VDDPCI
PCI [1-7]
VDDPCI
USBCLK [0:1]
VDDUSB
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07207 Rev. *A
Revised December 08, 2002
1 page  
CY2280
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Notes:
4. Electrical parameters are guaranteed with these operating conditions.
5. Crystal Inputs have CMOS thresholds.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Switching Characteristics[6, 7]
Parameter Output
t1 All
t2 CPUCLK,
APIC
Description
Output Duty Cycle[8]
CPU and APIC Clock
Rising and Falling Edge
Rate
Test Conditions
t1 = t1A ÷ t1B
Between 0.4V and 2.0V
-1,-11S,
-21S
t2
PCICLK PCI Clock Rising and Between 0.4V and 2.4V
-1,-11S,
Falling Edge Rate
-21S
t2 USBCLK, USB, REF Rising and Between 0.4V and 2.4V
REF
Falling Edge Rate
t3
CPUCLK CPU Clock Rise Time Between 0.4V and 2.0V
-1,-11S,
-21S
t4
CPUCLK CPU Clock Fall Time Between 2.0V and 0.4V
-1,-11S,
-21S
t5 CPUCLK CPU-CPU Clock Skew Measured at 1.25V
t6 CPUCLK, CPU-PCI Clock Skew[9] Measured at 1.25V for 2.5V -1,-11S,
PCICLK
clocks, and at 1.5V for 3.3V -21S
clocks
t7 PCICLK, PCI-PCI Clock Skew Measured at 1.5V
PCICLK
t8
CPUCLK, CPU-APIC Clock
APIC
Skew[10]
Measured at 1.25V for 2.5V
clocks
-21S
t9
APIC
APIC-APIC Clock Skew Measured at 1.25V
t10 CPUCLK Cycle-Cycle Clock Jitter Measured at 1.25V
-1,-11S,
-21S
t11 PCICLK Cycle-Cycle Clock Jitter Measured at 1.5V
t12 CPUCLK, Power-up Time
PCICLK
CPU, PCI clock stabilization from
power-up
Notes:
7. All parameters specified with loaded outputs.
8. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
9. PCI lags CPU for -11S and -21S options.
10. APIC lags CPU for -21S option.
Min. Max. Unit
Min.
45
1.0
Typ.
50
Max.
55
4.0
Unit
%
V/ns
1.0 4.0 V/ns
0.5 2.0 V/ns
0.4 1.6 ns
0.4 1.6 ns
100 175
1.5 4.0
ps
ns
250 ps
2.0 4.5 ns
100 175
200 250
ps
ps
250 500
3
ps
ms
Document #: 38-07207 Rev. *A
Page 5 of 12
5 Page 
Package Diagram
48-Lead Shrunk Small Outline Package O48
CY2280
51-85061-B
Document #: 38-07207 Rev. *A
Page 11 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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