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PDF CXP85840A Data sheet ( Hoja de datos )
| Número de pieza | CXP85840A | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP85840A/85848A/85856A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP85840A/85848A/85856A are the CMOS 8-bit
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time-base
timer, closed caption decoder, data slicer, on-screen
display function, I2C bus interface, PWM output,
remote control reception circuit, HSYNC counter and
watchdog timer, besides the basic configurations of
8-bit CPU, ROM, RAM, I/O ports.
The CXP85840A/85848A/85856A also provide a
power-on reset function and sleep function that
enables to lower the power consumption.
64 pin SDIP (Plastic)
64 pin QFP (Plastic)
Features
• A wide instruction set (213 instructions) which covers
Structure
Silicon gate CMOS IC
various types of data
– 16-bit operation/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle 333ns at 12MHz operation
• Incorporated ROM
40K bytes (CXP85840A)
48K bytes (CXP85848A)
56K bytes (CXP85856A)
• Incorporated RAM
2176 bytes (Excludes closed caption decoder and VRAM for on-screen display)
• Peripheral functions
– A/D converter
8-bit 6-channel successive approximation method
(Conversion time of 26.7µs at 12MHz)
– Serial interface
8-bit clock sync type, 1 channel
– Timer
8-bit timer
8-bit timer/counter
19-bit time-base timer
– Closed caption decoder
Data slicer
Corresponds to FCC (EDS supported), 8 × 13 dots, 192 character types
15 character colors, 4 lines × 34 characters
frame background 15 colors/ half blanking
italic, underline, vertical scrolling
– On-screen display (OSD) function 12 × 16 dots, 192 character types, 15 character colors
2 lines × 24 characters
frame background 8 colors/ half blanking
background on full screen 15 colors/ half blanking
edging and vertical scrolling for every line
jitter elimination circuit
sprite OSD, 12 × 16 dots, 1 screen, 8 colors for every dot
– I2C bus interface
– PWM output
8 bits, 8 channels
– Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
– HSYNC counter
2 channels
– Watchdog timer
• Interruption
15 factors, 15 vectors, multi-interruption possible
• Standby mode
Sleep
• Package
64-pin plastic SDIP/QFP
• Piggyback/evaluator
CXP85890A 64-pin ceramic PSDIP (Supports custom font)
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97739A86
1 page  
CXP85840A/85848A/85856A
Pin Description
Symbol
PA0/AN0
to
PA5/AN5
PA6/VSYNC
PA7/HSYNC
PB0 to PB5
I/O
I/O/
Analog input
I/O/Input
I/O/Input
I/O
PB6/INT1
I/O/Input
PC0 to PC7
I/O
PD0/INT2
PD1/SCK
PD2/SO
PD3/SI
PD4/HS0
PD5/HS1
PD6/RMC
PD7/EC
PE0/TO
PE1
I/O/Input
I/O/I/O
I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Output
I/O
PE2/INT0
I/O/Input
PF0/PWM0
to
PF3/PWM3
Output/Output
PF4/SCL0/PWM4
PF5/SCL1/PWM5
Output/I/O
PF6/SDA0/PWM6
PF7/SDA1/PWM7
Output/I/O
R, G, B, I, YS, YM Output
Description
(Port A)
8-bit I/O port. I/O
can be set in a unit
of single bits.
(8 pins)
Analog inputs to A/D converter.
(6 pins)
OSD display vertical sync signal input.
OSD display horizontal sync signal input.
(Port B)
7-bit I/O port. I/O can be set in a unit of single bits.
(7 pins)
External interruption request input.
Active at the falling edge.
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
External interruption request input.
Active at the falling edge.
(Port D)
8-bit I/O port.
I/O can be set in a
unit of single bits.
Can drive 12mA
synk current.
(8 pins)
Serial clock I/O.
Serial data output.
Serial data input.
HSYNC counter (CH0) input.
HSYNC counter (CH1) input.
Remote control reception circuit input.
External event input for timer/counter.
(Port E)
3-bit I/O port.
I/O can be set in a
unit of single bits.
(3 pins)
Rectangular wave output for timer/counter
External interruption request input.
Active at the falling edge.
(Port F)
8-bit output port
8-bit PWM output. (8 pins)
and large current
(12mA) N-channel
open drain output. I2C bus interface transfer clock I/O.
Lower 4 bits are (2 pins)
medium drive voltage
(12V); upper 4 bits
are 5V drive.
(8 pins)
I2C bus interface transfer data I/O.
(2 pins)
6-bit OSD display output. (6 pins)
–5–
5 Page 
CXP85840A/85848A/85856A
Absolute Maximum Ratings
(Vss = 0V reference)
Item
Symbol
Ratings
Unit
Remarks
Supply voltage
Input voltage
Output voltage
VDD
VIN
VOUT
–0.3 to +7.0
–0.3 to +7.0∗1
–0.3 to +7.0∗1
V
V
V
Medium drive output voltage
VOUTP
–0.3 to +15.0
V PF0 to PF3 pins
High level output current
IOH
–5 mA
High level total output current ∑IOH
–50 mA Total of all output pins
Low level output current
IOL
IOLC
15
mA
Ports excluding large current outputs
(value per pin)
20
mA
Large current output ports
(value per pin∗2)
Low level total output current ∑IOL
100 mA Total of all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
1000
600
mW SDIP-64P-01
mW GFP-64P-L01
∗1 VIN and VOUT should not exceed VDD + 0.3V.
∗2 The large current output port is Port D (PD) and Port F (PF).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
Recommended Operating Conditions
(Vss = 0V reference)
Item
Symbol Min.
Max. Unit
Remarks
4.5
5.5
V
Guaranteed operation range for 1/2 and
1/4 frequency dividing clocks
Supply voltage
VDD 3.5
5.5
V
Guaranteed operation range for 1/16
frequency dividing clock or sleep mode
2.5 5.5 V Guaranteed data hold range for stop mode∗1
Data slicer supply voltage CVDD 4.5
5.5 V ∗5
VIH 0.7VDD
VDD
V ∗2
High level input voltage VIHS 0.8VDD
VDD
V ∗3
VIHEX VDD – 0.4 VDD + 0.3 V EXTAL pin∗4
VIL
0
0.3VDD
V ∗2
Low level input voltage VILS
0
0.2VDD
V ∗3
VILEX
–0.3
0.4
V EXTAL pin∗4
Operating temperature
Topr
–20
+75 °C
∗1 This device does not enter the stop mode.
∗2 PA, PB, PC, PE0 to PE1, SCL0 to 1, SDA0 to 1 pins.
∗3 INT2, SCK, SO, SI, HS0, HS1, RMC, EC, INT1, HSYNC, VSYNC, RST pins.
∗4 Specifies only during external clock input.
∗5 CVDD and VDD should be set to the same voltage.
– 11 –
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CXP85840A.PDF ] | |
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