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PDF CXP85324A Data sheet ( Hoja de datos )
| Número de pieza | CXP85324A | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP85324A/85332A/85340A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP85324A/85332A/85340A are a highly
integrated microcomputers composed of a 8-bit
CPU, ROM, RAM, and I/O ports. These chips feature
many other high-performance circuits in a single-chip
CMOS design, including an A/D converter, serial
interface, timer/counter, time-base timer, on-screen
display function, I2C bus interface, PWM output,
remote control reception circuit, HSYNC counter,
power supply frequency counter, and watchdog
timer.
Futhermore, the CXP85324A/85332A/85340A
series provides power-on reset and sleep functions
which enable to lower power consumption.
64 pin SDIP (PIastic)
Structure
Silicon gate CMOS IC
64 pin QFP (PIastic)
Features
• A wide instruction set (213 instructions) which covers various types of data
– 16-bit operation/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle 1µs at 4MHz (4MHz version)
0.5µs at 8MHz (8MHz version)
• Incorporated ROM capacity 24K bytes (CXP85324A)
32K bytes (CXP85332A)
40K bytes (CXP85340A)
• Incorporated RAM capacity 576 bytes
• Peripheral functions
– A/D converter
8-bit, 4-channel successive approximation method
(Conversion time of 40µs at 4MHz and 8MHz)
– Serial interface
8-bit clock sync type, 1 channel
– Timer
8-bit timer
8-bit timer/counter
19-bit time-base timer
– On screen display (OSD) function 12 × 18 dots, 256 character types, 15 character colors,
12lines of 21 characters,
black frame output/half blanking, shadow, background
color on full screen/half blanking,
double scanning, jitter elimination circuit
– I2C bus interface
– PWM output
14 bits, 1 channel
8 bits, 8 channels
– Remote control reception circuit 8-bit pulse measurement circuit, 6-state FIFO
– HSYNC counter
– Power supply frequency counter
– Watchdog timer
• Interruption
14 factors, 14 vectors, multi-interruption possible
• Standby mode
SLEEP
• Package
64-pin plastic SDIP/QFP
• Piggyback/evaluator
CXP85300A 64-pin ceramic PSDIP/PQFP
CXP85390 64-pin ceramic PSDIP (accommodates custom font)
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93X37B86
1 page  
CXP85324A/85332A/85340A
Pin Description
Symbol
PA0 to PA5
PA6/VSYNC
PA7/HSYNC
I/O
I/O
I/O/Input
I/O/Input
PB0 to PB7
I/O
PC0 to PC7 I/O
PD0/INT2
I/O/Input
PD1/SCK
PD2/SO
PD3/SI
PD4/HSI
PD5/ACI
PD6/RMC
PD7/EC
I/O/I/O
I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input
PE0/INT0
PE1/INT1
Input/Input
PE2/AN0
to
PE5/AN3
Input/Input
PE6/PWM
Output/Output
PE7/TO
Output/Output
PF0/PWM0
to
PF3/PWM3
Output/Output
PF4/PWM4/
SCL0
PF5/PWM5/
SCL1
Output/Output/
I/O
PF6/PWM6/
SDA0
PF7/PWM7/
SDA1
Output/Output/
I/O
R, G, B, I, YS, YM Output
Description
(Port A)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
OSD display vertical synchronization signal input pin.
OSD display horizontal synchronization signal input pin.
(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
Input pin for external interruption request.
Active when falling edge.
(Port D)
8-bit I/O port. I/O
can be set in a unit
of single bits.
12mA sink current
drive possible.
(8 pins)
Serial clock I/O pin.
Serial data output pin.
Serial data input pin.
HSYNC counter input pin.
Power supply frequency counter input pin.
Remote control reception circuit input pin.
External event input pin timer/counter.
(Port E)
8-bit port. Lower
6 bits are for inputs;
upper 2 bits are for
outputs.
(8 pins)
Input pin for external interruption request.
Active when falling edge.
(2 pins)
Analog input pin for A/D converter.
(4 pins)
14-bit PWM output pin.
(CMOS output)
Timer/counter rectangular wave output pin.
(Port F)
8-bit output port.
Large current
(12mA) N-ch open
drain output.
Lower 4 bits are
mid-voltage drive
(12V); upper 4 bits
are 5V drive.
(8 pins)
8-bit PWM output pin.
(8 pins)
I2C bus interface transfer clock I/O pin.
(2 pins)
I2C bus interface transfer data I/O pin.
(2 pins)
OSD display 6-bit output pin. (6 pins)
–5–
5 Page 
CXP85324A/85332A/85340A
Absolute Maximum Ratings
(Vss = 0V reference)
Item
Symbol
Ratings
Unit
Remarks
Supply voltage
Input voltage
Output voltage
VDD
VIN
VOUT
–0.3 to +7.0
–0.3 to +7.0∗1
–0.3 to +7.0∗1
V
V
V
Mid-voltage drive output voltage
VOUTP
–0.3 to +15.0
V PF0 to PF3 pins
High level output current
IOH –5 mA
High level total output current
∑IOH
–50 mA Total of all output pins
Low level output current
IOL
15
mA
Ports excluding large current
output (value per pin)
IOLC
20
mA
Large current output port
(value per pin)∗2
Low level total output current
∑IOL
130 mA Total of all output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Allowable power dissipation
1000
mW SDIP
PD
600 mW QFP
∗1 VIN and VOUT should not exceed VDD + 0.3V.
∗2 The large current output port is Port D (PD) and Port F (PF).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
Recommended Operating Conditions
(Vss = 0V reference)
Item
Symbol Min.
Max. Unit
Remarks
4.5
5.5
V
Guaranteed operation range for 1/2 and 1/4
frequency dividing modes.
Supply voltage
VDD
3.5
5.5
V
Guaranteed operation range for 1/16 frequency
dividing mode or SLEEP mode.
2.5 5.5 V Guaranteed data hold range for STOP mode.∗1
High level
input voltage
VIH
0.7VDD
VDD
V ∗2
VIHS
0.8VDD
VDD
V ∗3
VIHEX VDD – 0.4 VDD + 0.3 V EXTAL pin∗4
Low level
input voltage
VIL
VILS
VILEX
0
0
–0.3
0.3VDD
0.2VDD
0.4
V ∗2
V ∗3
V EXTAL pin∗4
Operating temperature Topr –20 +75 °C
∗1 This device does not enter the STOP mode.
∗2 PA, PB, PC, PE2 to PE5, SCL0, SCL1, SDA0, SDA1 pins
∗3 INT2, SCK, SI, HSI, ACI, RMC, EC, INT0, INT1, HSYNC, VSYNC, RST pins.
∗4 Specifies only during external clock input.
– 11 –
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CXP85324A.PDF ] | |
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