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PDF CXP842P24 Data sheet ( Hoja de datos )
| Número de pieza | CXP842P24 | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP842P24
CMOS 8-bit Single Chip Microcomputer
Description
The CXP842P24 is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer/counter, and remote control
reception circuit besides the basic configurations of
8-bit CPU, ROM, RAM, and I/O port.
The CXP842P24 also provides a power-on reset
function and a sleep/stop function that enables lower
power consumption.
This IC is the PROM-incorporated version of the
CXP84224 with built-in mask ROM. This provides the
additional feature of being able to write directly into
the program. Thus, it is most suitable for evaluation
use during system development and for small-quantity
production.
64 pin SDIP (Plastic)
Structure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation
• Incorporated PROM capacity
24K bytes
• Incorporated RAM capacity
624 bytes
• Peripheral functions
— A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronization, 1 channel
— Timer
8-bit timer
8-bit timer/counter
19-bit time base timer
16-bit capture timer/counter
— Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO
— PWM output
14 bits, 1 channel
• Interruption
14 factors, 14 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
64-pin plastic SDIP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93839A7X-PS
1 page  
Symbol
I/O
PG0 to PG2 I/O
PI0/INT0
to
PI3/INT3
PI4 to PI6
EXTAL
XTAL
RST
AVREF
AVss
VDD
Vpp
Vss
I/O/Input
I/O
Input
Output
I/O
Input
CXP842P24
Description
(Port G)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-
up resistor can be set through the software in a unit of 4 bits.
(3 pins)
(Port I)
7-bit I/O ports. I/O can be set in a unit of single
bits. Incorporation of pull-up resistor can be set
through the software in a unit of 4 bits.
(7 pins)
External interruption
request inputs.
Crystal connectors for system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to XTAL.
Low-level active, system reset.
Reference voltage input for A/D converter.
A/D converter GND.
Positive power supply.
Positive power supply for incorporated PROM writing.
Connect to VDD during normal operation.
GND
–5–
5 Page 
CXP842P24
Recommended Operating Conditions
(Vss = 0V reference)
Item
Symbol Min.
Max. Unit
Remarks
4.5 5.5
High-speed mode guaranteed operation
range∗1
Supply voltage
VDD 3.5
5.5
V Low-speed mode guaranteed operation
range∗1
High level input
voltage
Low level input
voltage
2.5 5.5
Guaranteed data hold range during stop
Vpp
Vpp = VDD
V ∗5
VIH 0.7VDD VDD V ∗2
VIHS
0.8VDD
VDD
V Hysteresis input∗3
VIHEX VDD – 0.4 VDD + 0.3 V EXTAL∗4
VIL 0 0.3VDD V ∗2
VILS 0 0.2VDD V Hysteresis input∗3
VILEX
–0.3
0.4 V EXTAL∗4
Operating temperature Topr
–10
+75 °C
∗1 High-speed mode is 1/2 frequency demultiplication clock selection; low-speed mode is 1/16 frequency
demultiplication clock selection.
∗2 Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF, PG, PI4 to PI6).
∗3 Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2,
INT3.
∗4 Specifies only during external clock input.
∗5 Vpp and VDD should be set to the same voltage.
– 11 –
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CXP842P24.PDF ] | |
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