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PDF CXP836P61 Data sheet ( Hoja de datos )
| Número de pieza | CXP836P61 | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CMOS 8-bit Single Chip Microcomputer
CXP836P60
CXP836P61
Description
The CXP836P60/836P61 is a CMOS 8-bit single
chip microcomputer integrating on a single chip an
A/D converter, serial interface, timer/counter, time-
base timer, sub timer/counter, LCD controller/driver
and remote control reception circuit besides the basic
configurations of 8-bit CPU, PROM, RAM, and I/O
port.
The CXP836P60/836P61 also provides a sleep/stop
function that enables lower power consumption.
The CXP836P60 and CXP836P61 are the PROM-
incorporated version of the CXP83508/83512/83516/
83620/83624 and CXP83509/83513/83517/83621/83625
with built-in mask ROM, and they are able to write
directly into the program. Thus, it is most suitable for
evaluation use during system development and for
small-quantity production.
CXP836P60
80 pin QFP (Plastic) 80 pin LQFP (Plastic)
CXP836P61
80 pin QFP (Plastic)
Features
• Wide-range instruction system (213 instructions) to
cover various types of data.
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle 400ns at 10MHz operation (4.5 to 5.5V)
1µs at 4MHz operation (2.7 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated PROM capacity 60K bytes
• Incorporated RAM capacity 736 bytes (includes LCD display data area and serial interface RAM)
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation method
(Conversion time of 12.4µs/10MHz)
— Serial interface
Incorporated buffer RAM
(Auto transfer for 1 to 32 bytes), 1 channel
8-bit clock synchronized type (MSB/LSB first selectable), 1 channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time-base timer,
Sub timer/counter
— LCD controller/driver
Maximum 128 segment display possible (during 1/4 duty)
4 common output, 32 segment output
Display method static, 1/2, 1/3, 1/4 duty
Bias method 1/2, 1/3 bias
— Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO
• Interruption
14 factors, 14 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
80-pin plastic QFP/LQFP
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98342B96
1 page  
Pin Assignment (Top View) CXP836P61 (QFP package)
CXP836P60, CXP836P61
PE5/TO
PE6/ADJ
PB0
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PH0/INT4
PA0/AN0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PD4/SEG20
PD3/SEG19
PD2/SEG18
PD1/SEG17
PD0/SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Note) Do not make any connections to Vpp (Pin 73).
–5–
5 Page 
Pin
Port I
PI0/TX
PI1/TEX
PI1/TEX
CXP836P60, CXP836P61
Circuit format
IP IP
After a reset
TEX oscillation control circuit
"1" after a reset
Internal data bus
RD (Port I)
Internal data bus
RD (Port I)
Schmitt input
Clock input
Oscillation
halted port
input
2 pins
PI0/TX
PD0/SEG16
to
PD7/SEG23
PF0/SEG24
to
PF7/SEG31
16 pins
Port D
Port F
Port D, F data
Port/segment output select
"0" after a reset
Segment data
Segment
driver
Segment
SEG0 to SEG15
VCH
16 pins
VCL
Common
VDD
COM0 to COM3
VLC1
VLC2
4 pins
VLC3
– 11 –
Segment
Output
(VDD level)
VDD level
VDD level
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXP836P61.PDF ] | |
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