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PDF CXP82840 Data sheet ( Hoja de datos )
| Número de pieza | CXP82840 | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP82832/82840/82852/82860
CMOS 8-bit Single Chip Microcomputer
Description
The CXP82832/82840/82852/82860 is a CMOS 8-
bit single chip microcomputer integrating on a single
chip an A/D converter, serial interface, timer/counter,
time base timer, capture timer/counter, fluorescent
display panel controller/driver, remote control
reception circuit, and PWM output besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O port.
The CXP82832/82840/82852/82860 also provides
sleep/stop function that enables lower power
consumption.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation
(122µs at 32kHz operation)
• Incorporated ROM capacity
32K bytes (CXP82832)
40K bytes (CXP82840)
52K bytes (CXP82852)
60K bytes (CXP82860)
• Incorporated RAM capacity
1536 bytes (including fluorescent display area)
• Peripheral functions
— A/D converter
8 bits, 8 channels, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface
8-bit, 8-stage FIFO incorporated
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronized type, 1 channel
— Timers
8-bit timer, 8-bit timer/counter, 19-bit time base timer
16-bit capture timer/counter, 32kHz timer/counter
— Fluorescent display panel controller/driver Supports the universal grid fluorescent display panel.
High voltage drive output port of 56 pins (40V)
Maximum of 640 segments display possible
Display timing number of 1 to 20
Dimmer function
Incorporated pull-down resistor (Mask option)
Hardware key scan function (Maximum of 16 × 8 key matrix
supportable)
— Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
— PWM output
14 bits, 1 channel
• Interruption
16 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP
• Piggyback/evaluation chip
CXP82800 100-pin ceramic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94Y08B74
1 page  
CXP82832/82840/82852/82860
Pin code
PG0/A39
to
PG7/A32
PH0/A31
to
PH7/A24
A16 to A23
G0/A0
to
G15/A15
VFDP
EXTAL
XTAL
TEX
TX
RST
NC
AVREF
AVSS
VDD
VSS
I/O
Output/Output
Output/Output
Output
Output/Output
Input
Output
Input
Output
Input
Input
Functions
(Port G)
8-bit output port.
(8 pins)
FDP segment signal (anode
connection) outputs.
(8 pins)
(Port H)
8-bit output port.
(8 pins)
FDP segment signal (anode
connection) outputs.
(8 pins)
FDP segment signal (anode connection) outputs.
(8 pins)
Outputs for FDP timing signals (grid connection)/segment signals (anode
connection).
(16 pins)
FDP voltage supply when incorporated pull-down (PD) resistor is set by
mask option.
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
Crystal connectors for 32kHz timer/counter clock oscillation. For usage
as event input, input to TEX, and open TX.
Low-level active, system reset
NC. Under normal operation, connect to VDD.
Reference voltage input for A/D converter.
A/D converter GND.
VCC supply.
GND.
–5–
5 Page 
CXP82832/82840/82852/82860
Recommended Operating Conditions
(Vss = 0V reference)
Item
Supply voltage
Symbol Min.
4.5
VDD 3.5
2.7
Max.
5.5
5.5
5.5
Unit Remarks
Guaranteed operation range during
V high-speed mode
(1/2 and 1/4 frequency dividing clock)
Guaranteed operation range low-speed
V mode or SLEEP mode
(1/16 frequency dividing clock)
V
Guaranteed operation range with TEX
clock
High level input
voltage
Low level input
voltage
Operating temperature
VIH
VIHS
VIHEX
VIL
VILS
VILEX
Topr
2.5 5.5 V Guaranteed data hold range during STOP
0.7VDD
VDD
V ∗1
0.8VDD
VDD
V Hysteresis input∗2
VDD – 0.4 VDD + 0.3 V EXTAL∗3
0
0.3VDD
V ∗1
0
0.2VDD
V Hysteresis input∗2
–0.3
0.4 V EXTAL∗3
–20 +75 °C
∗1 Value for each pin of normal input port (PA, PB4, PB7, PC).
∗2 Value of the following pins: RST, CINT, CS0, SCK0, SCK1, SI0, SI1, EC0/INT0, EC1/INT1, INT2,
INT3/NMI, RMC.
∗3 Specifies only during external clock input.
– 11 –
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CXP82840.PDF ] | |
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