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PDF CXP824P40A Data sheet ( Hoja de datos )
| Número de pieza | CXP824P40A | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP824P40A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP824P40A is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer counter, fluorescent display tube,
controller/driver, remote control reception circuit, CTL
duty detection circuit, 14-bit PWM output and high-
speed output circuit besides the basic configurations
of 8-bit CPU, PROM, RAM, and I/O port.
The CXP824P40A also provides sleep/stop function
that enables lower power consumption.
CXP824P40A is the PROM-incorporated version of
the CXP82440A with built-in mask ROM. This
provides the additional feature of being able to write
directly into the program. Thus, it is most suitable for
evaluation use during system development and for
small-quantity production.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation
122µs at 32kHz operation
• Incorporated PROM capacity
40K bytes
• Incorporated RAM capacity
1120 bytes (including fluorescent display area)
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface
Incorporated 8-bit, 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock sync type, 1 channel
— Timers
8-bit timer, 8-bit timer/counter, 19-bit time base timer
16-bit capture timer/counter, 32kHz timer/counter
— Fluorescent display tube controller/driver Maximum of 384 segments display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
On-chip pull-down resistor (Mask option)
Hardware key scan function
(Maximum of 16 × 8 key matrix compatible)
— Remote control receiving circuit
Incorporated noise elimination circuit
8-bit measurement counter with on-chip 6-stage FIFO
— PWM output
14 bits, 1 channel
— CTL duty detection circuit
— High-speed output circuit
RTG 4 pins
• Interruption
19 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94Z17-PP
1 page  
CXP824P40A
Pin code
I/O
PH0 to PH7 I/O
PI0/S16
to
PI7/S23
T8/S31
to
T15/S24
T0 to T7
VFDP
EXTAL
XTAL
TEX
TX
RST
AVREF
AVSS
VDD
Vpp
VSS
Output/Output
Output/Output
Output
Input
Output
Input
Output
Input
Input
Functions
(Port H)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
(Port I)
8-bit output ports.
(8 pins)
FDP segment signal outputs.
Outputs for FDP timing (digit) signals/segment signals.
FDP timing signal outputs.
FDP voltage supply when incorporated resistor is set by mask option.
Crystal connectors system clock oscillation. When the clock is supplied
externally, input to EXTAL; opposite phase clock should be input to
XTAL.
Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz
crystal oscillator between TEX and TX. For usage as event input, attach
clock source to TEX, and open TX.
Low-level active, system reset.
Reference voltage input for A/D converter.
A/D converter GND.
Vcc supply.
VCC supply for incorporated PROM writing.
Connect to VDD during normal operation.
GND.
–5–
5 Page 
CXP824P40A
Recommended Operating Conditions
(Vss = 0V reference)
Item
Symbol Min.
Max. Unit
Remarks
4.5
5.5
V
High-speed mode
Guaranteed operation range
Supply voltage
VDD
3.5
5.5
V
Low-speed mode
Guaranteed operation range
2.7
5.5
V
Guaranteed operation range with TEX
clock
High level input
voltage
Low level input
voltage
2.5 5.5 V Guaranteed data hold range during STOP
Vpp
Vpp = VDD
V ∗4
VIH
0.7VDD
VDD
V ∗1
VIHS
0.8VDD
VDD
V Hysteresis input∗2
VIHEX VDD – 0.4 VDD + 0.3 V EXTAL∗3
VIL
0
0.3VDD
V ∗1
VILS
0
0.2VDD
V Hysteresis input∗2
VILEX
–0.3
0.4 V EXTAL∗3
Operating temperature Topr –10 +75 °C
∗1) Value for each pin of normal input port (PA, PB4, PC, PG, PH).
∗2) Value of the following pins: RST, CINT, CS0, SCK0, SCK1, SI0, SI1, EC0/INT0, EC1/INT1, INT2,
INT3/NMI, RMC, CTL.
∗3) Specifies only during external clock input.
∗4) Vpp and VDD should be set a same voltage.
– 11 –
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CXP824P40A.PDF ] | |
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