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PDF CXP80732A Data sheet ( Hoja de datos )
| Número de pieza | CXP80732A | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP80732A/80740A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP80732A/80740A is a CMOS 8-bit micro-
computer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, VISS/VASS
circuit, 32kHz timer/event counter, remote control
receiving circuit, VCR vertical sync separation circuit
and the measuring circuit which measure signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.
Also CXP80732A/80740A provides sleep/stop function
which enables to lower power consumption and ultra-
low speed instruction mode in 32kHz operation.
100 pin QFP (PIastic)
Structure
Silicon gate CMOS IC
100 pin LQFP (PIastic)
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction
• Minimum instruction cycle
During operation 250ns/16MHz (Supply voltage 4.5 to 5.5V)
During operation 122µs/32kHz
• Incorporated ROM capacity 32K bytes (CXP80732A)
40K bytes (CXP80740A)
• Incorporated RAM capacity 800 bytes
• Peripheral functions
— A/D converter
8-bit, 12-channel, successive approximation system
(Conversion time 20.0µs/16MHz)
— Serial interface
Incorporated 8-bit and 8-stage FIFO, 1-channe
(1 to 8 bytes auto transfer)
8-bit serial I/O, 1-channel
— Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer,
32kHz timer/counter
— High precision timing pattern generator PPG 19 pins 32-stage programmable
RTG 5-pins 2-channel
— PWM/DA gate output
12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)
— Servo input control
Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit
Incorporated 26-bit and 8-stage FIFO
— PWM output
14-bit, 1-channel
— VISS/VASS circuit
Pulse duty auto detection circuit
— Remote control receiving circuit
8-bit pulse measuring counter, 6-stage FIFO
• Interruption
21 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
100-pin plastic QFP/LQFP
• Piggyback/evaluation chip
CXP87700 100-pin ceramic QFP/LQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94Z09-ST
1 page  
CXP80732A/80740A
Pin Description
Symbol
I/O
PA0/PPO0
to
PA7/PPO7
Output/
Real time
Output
PB0/PPO8
to
PB7/PPO15
Output/
Real time
Output
PC0/PPO16
to
PC2/PPO18
PC3/RTO3
to
PC7/RTO7
I/O/
Real time
Output
I/O/
Real time
Output
PD0 to PD7 I/O
PE0/INT0
Input/input
PE1/EC/INT2 Input/input/input
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
AN0 to AN3
PF0/AN4
to
PF3/AN7
PF4/AN8
to
PF7/AN11
SCK0
SO0
SI0
CS0
Output/output
Output/output
Output/output
Output/output
Output/output
Output/output
Input
Input/input
Output/input
I/O
Ouput
Input
Input
Description
(Port A)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
(Port B)
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
Programmable pattern generator (PPG)
output.
Functions as high precision real time
pulse output port.
(19 pins)
(Port C)
8-bit I/O port, enables to
specify I/O by bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)
Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)
(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current.
(8 pins)
Input pin to request external interruption.
Active when falling edge.
(Port E)
8-bit port. Lower 2 bits are
input pins and upper 6 bits
are output pins.
(8 pins)
External event Input pin to request
input pin for external interruption.
timer/counter. Active when falling edge.
PWM output pins.
(2 pins)
DA gate pulse output pins.
(4 pins)
Analog input pins to A/D converter. (12 pins)
(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)
Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.
Serial chip select (CH0) input pin.
–5–
5 Page 
CXP80732A/80740A
Pin
Circuit format
When reset
SCK0
1 pin
Internal serial clock
from SIO
SCK0 output enable
External serial clock to SIO
Schmitt input
IP
Hi-Z
EXTAL
XTAL
2 pins
EXTAL
XTAL
TEX
TX
TEX
2 pins
TX
• Shows the circuit
composition during
IP oscillation.
• Feedback resistor is
Oscillation
removed during stop.
XTAL becomes
"H" level.
32kHz
• Shows the circuit
timer counter composition during
oscillation.
IP • Feedback resistor is
removed during 32kHz
oscillation circuit stop
Oscillation
by software.
At this time TEX pin
outputs "L" level and TX
pin outputs "H" level.
RST
1 pin
Mask option
Pull-up resistor
Schmitt input
OP
IP
L level
MP
1 pin
IP CPU mode
Hi-Z
– 11 –
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet CXP80732A.PDF ] | |
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