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PDF CXP750010 Data sheet ( Hoja de datos )
| Número de pieza | CXP750010 | |
| Descripción | CMOS 8-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CMOS 8-bit Single Chip Microcomputer
CXP750096/750010
CXP750097/750011
Description
The CXP750096/750010, CXP750097/750011 are the
CMOS 8-bit single chip microcomputer integrating on a
single chip an A/D converter, serial interface, timer/
counter, time-base timer, on-screen display function, I2C
bus interface, PWM output, remote control reception
circuit, HSYNC counter, watchdog timer, 32kHz timer/
counter besides the basic configurations of 8-bit CPU,
ROM, RAM, I/O ports.
The CXP750096/750010, CXP750097/750011 also
provide a sleep function that enables to lower the power
consumption.
64 pin SDIP (Plastic)
64 pin QFP (Plastic)
Features
52 pin SDIP (Plastic)
• A wide instruction set (213 instructions) which covers
various types of data
– 16-bit operation/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle 167ns at 24MHz operation
122µs at 32kHz operation
• Incorporated ROM 96K bytes (CXP750096/750097)
120K bytes (CXP750010/750011)
• Incorporated RAM 2496 bytes
(Excludes VRAM for on-screen display)
• Peripheral functions
– A/D converter
8-bit 6-channel successive approximation method
(Conversion time of 3.25µs at 16MHz)
Structure
Silicon gate CMOS IC
– Serial interface
8-bit clock sync type, 1 channel
– Timer
8-bit timer
8-bit timer/counter
19-bit time-base timer
32 kHz timer/counter
– On-screen display (OSD) function 24 × 32 dots, 512 character types,
15 character colors, 2 lines × 32 characters,
frame background 8 colors/ half blanking,
background on full screen 15 colors/ half blanking
edging/ shadowing/ rounding for every line,
background with shadow for every character, double scanning,
sprite OSD,
24 × 32 dots, 1 screen, 8 colors for every dot
– I2C bus interface
– PWM output
8 bits, 8 channels
14 bits, 1 channel
– Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO
– HSYNC counter
2 channels
– Watchdog timer
• Interruption
13 factors, 13 vectors, multi-interruption possible
• Standby mode
Sleep
• Package
64-pin plastic SDIP/QFP, 52-pin plastic SDIP
• Piggyback/evaluator
CXP750000 64-pin ceramic PQFP/PSDIP (Supports custom font)
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98767-PS
1 page  
Pin Assignment (Top View) 52-pin SDIP
EC/PD7
RMC/PD6
HS1/PD5
HS0/PD4
SI/PD3
SO/PD2
SCK/PD1
INT2/PD0
HSYNC/PA7
VSYNC/PA6
RST
VSS
XTAL
EXTAL
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
PB7
PB6
PB5
PB4
PB3
INT1/PG7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CXP750096/750010, CXP750097/750011
52 PF0/PWM0
51 PF1/PWM1
50 PF2/PWM2
49 PF3/PWM3
48 PF4/SCL0
47 PF5/SCL1/PWM4
46 PF6/SDA0
45 PF7/SDA1/PWM5
44 PE0/TO/ADJ
43 PE1/PWM
42 PE2/TEX/INT0
41 PE3/TX
40 VSS
39 VDD
38 NC
37 EXLC
36 XLC
35 PE4/YM
34 PE5/YS
33 PE6/I
32 B
31 G
30 R
29 PB0
28 PB1
27 PB2
Note)
1. NC (Pin 38) is left open.
2. Vss (Pins 12 and 40) are both connected to GND.
–5–
5 Page 
CXP750096/750010, CXP750097/750011
Pin Circuit format
Port F
SCL, SDA
I2C bus enable
∗
PF4/SCL0
PF5/SCL1/PWM4
PF6/SDA0
PF7/SDA1/PWM5
4 pins
PWM4, PWM5
Port F function selection
“0” after a reset
Port F data
“1” after a reset
Internal data bus
RD (Port F) Schmitt input
SCL, SDA
(I2C bus circuit)
∗ Large current 12mA
IP
BUS SW
To internal I2C pins
(SCL1 for SCL0)
After a reset
Hi-Z
R
G
B
3 pins
EXLC
XLC
R, G, B
Output polarity
“0” after a reset
Oscillation control
EXLC
IP
Writing data to output
polarity register brings
output to active.
Hi-Z
IP OSD display clock
Oscillation
halted
2 pins
XLC
EXTAL
XTAL
2 pins
RST
1 pin
EXTAL
XTAL
IP
• Diagram shows the
circuit composition
during oscillation.
• Feedback resistor is
removed and XTAL is driven
at "H" level driving stop.
(This device does not enter the
stop mode.)
Pull-up resistor
OP Mask option
Schmitt input
– 11 –
Oscillation
Low level
(during a
reset)
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet CXP750010.PDF ] | |
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