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PDF CXP402 Data sheet ( Hoja de datos )
| Número de pieza | CXP402 | |
| Descripción | CMOS 4-bit Single Chip Microcomputer | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXP402
CMOS 4-bit Single Chip Microcomputer
For the availability of this product, please contact the sales office.
Description
The CXP402 is a CMOS 4-bit single chip micro-
computer which consists of 4-bit CPU, ROM, RAM,
8-bit timer, 8-bit timer/counter, 18-bit time-base timer,
LCD controller/driver, digital signal processor circuit
for CD player, 1-bit DAC and the like.
112 pin LQFP (Plastic)
Features
• Instruction cycle 1.89µs for 16.93MHz oscillation
• ROM capacity 6144 × 8 bits
• RAM capacity 400 × 4 bits
(Including stack and display area)
• LCD controller/driver (Enables to direct drive)
• 8-bit timer, 8-bit timer/event counter and 18-bit
time-base timer are incorporated; they are
independently controllable.
• Arithmetic and logical operations between the entire
RAM area, I/O area and the accumulator by means
of the memory mapped I/O.
• Entire ROM area can be referred by the table look-
up instruction.
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular
Velocity)
• Frame jitter free
• Allows relative rotational velocity readout
• Supports spindle external control
• Wide capture range playback mode
• Spindle rotational velocity following method
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• Servo auto sequencer
• Digital audio interface output
• Digital peak meter
Digital Filter, DAC and Analog Low-Pass Filter Blocks
• DBB (digital bass boost) function
• Digital de-emphasis
• Digital attenuation
• Zero detection function
• 8Fs oversampling digital filter
• S/N: 100dB or more
(master clock: 384Fs, typ.)
Logical value: 109dB
• THD + N: 0.007% or less
(master clock: 384Fs, typ.)
• Rejection band attenuation: –60dB or more
• 112-pin plastic LQFP
• Piggyback package (CXP401Z) available
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98924-PS
1 page  
CXP402
Symbol
XRSTO
FOK
LRCK
LRCKI
PCMD
PCMDI
BCK
BCKI
GTOP
XPCK
GFS
RFCK
C2PO
XROF
MNT3
MNT1
MNT0
C4M
DOUT
EMPH
WFCK
SCOR
SBSO
EXCK
AOUT1
AIN1
LOUT1
AOUT2
AIN2
LOUT2
RMC
XTAI
XTAO
NC
I/O Description
Output
Reset signal output. Active at low.
Input
Focus OK input.
Used for SENS output and servo auto sequencer.
Output
D/A interface LR clock output. (f = Fs)
Input
LR clock input.
Output
D/A interface serial data output.
Input
D/A interface serial data input.
Output
D/A interface bit clock output.
Input
D/A interface bit clock input.
Output
GTOP output.
Output
XPLCK output.
Output
GFS output.
Output
RFCK output.
Output
C2PO output.
Output
XRAOF output.
Output
MNT3 output.
Output
MNT1 output.
Output
MNT0 output.
Output
1/4 frequency division output of the oscillation input. (4.2336MHz for
16.3944MHz)
Output
Digital Out output.
Output
De-emphasis ON/OFF output. High is output for ON; low is output for OFF.
Output
WFCK output.
Output
Subcode sync detection output. Outputs a high signal when either
subcode sync S0 or S1 is detected.
Output
Sub P to W serial data output.
Input
SBSO serial clock input.
Output (Analog) Lch analog output.
Input (Analog) Lch operational amplifier input.
Output
Lch LINE output.
Output (Analog) Rch analog output.
Input (Analog) Rch operational amplifier
Output
Rch LINE output.
Input
Remote control receiver circuit input.
Input
Connect a crystal for system clock oscillation. When the clock is supplied
externally, input it to the XTAI pin and leave the XTAO pin open.
No connected.
–5–
5 Page 
CXP402
Absolute Maximum Ratings
(Vss = 0V reference)
Item
Supply voltage
LCD bias voltage
Input voltage
Output voltage
Symbol
VDD
VLC1, VLC2, VLC3
VIN
VOUT
Ratings
–0.3 to +7.0∗1
–0.3 to +7.0∗2
–0.3 to +7.0∗2
–0.3 to +7.0∗2
Unit
V
V
V
V
Remarks
High level output current
IOH
–5 mA Output pin (value per pin)
High level total output current ∑IOH
–70 mA Total of output pins
Low level output current
IOL
15 mA Output pin (value per pin)
Low level total output current ∑IOL
100 mA Total of output pins
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–40 to +125
°C
Allowable power dissipation PD
600 mW
∗1 The potential difference between analog power supplies AVDD, AVss, the oscillation power supplies XVDD,
XVss and VDD, Vss should be within ±0.3V.
∗2 VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended conditions. Exceeding those conditions may adversely affect the
reliability of the LSI.
Recommended Operation Conditions
(Vss = 0V reference)
Item
Symbol
Min.
Max.
Unit
Remarks
Supply voltage
VDD
3.4 5.25 V Operation guaranteed range
LCD bias voltage
VLC1,
VLC2,
VLC3
VSS
VDD
V
Liquid crystal power supply
range∗1
VIH
High level input voltage
VIHS
0.7VDD
0.8VDD
VDD
V
VDD V Hysteresis input∗2
Low level input voltage
Analog input voltage
VIL
VILS
VIA
0
0.3VDD
V
0
0.2VDD
V Hysteresis input∗2
0
VDD
V ∗3
Operating temperature Topr
–20 +75 °C
∗1 The optimal value depends on the characteristics of the used LCD element. Also, the LCD bias voltage is
biased to 1/3 the supply voltage by the resistor of approximately 20kΩ in the LSI.
∗2 RME, XRST, EXCK, FOK, SEIN, CNIN, VCKI, LRCKI, BCKI, PCMDI pins
∗3 CLTV, FILI, RF, VCTL, AIN1, AIN2, BAIS, ASYI pins
– 11 –
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CXP402.PDF ] | |
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