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PDF HS9-6617RH-Q Data sheet ( Hoja de datos )
| Número de pieza | HS9-6617RH-Q | |
| Descripción | Radiation Hardened 2K x 8 CMOS PROM | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HS-6617RH
August 1995
Radiation Hardened
2K x 8 CMOS PROM
Features
• Total Dose 1 x 105 RAD (Si)
• Latch-Up Free >1 x 1012 RAD (Si)/s
• Field Programmable
• Functionally Equivalent to HM-6617
• Pin Compatible with Intel 2716
• Low Standby Power 1.1mW Max
• Low Operating Power 137.5mW/MHz Max
• Fast Access Time 100ns Max
• TTL Compatible Inputs/Outputs
• Synchronous Operation
• On Chip Address Latches
• Three-State Outputs
• Nicrome Fuse Links
• Easy Microprocessor Interfacing
• Military Temperature Range -55oC to +125oC
Description
The Intersil HS-6617RH is a radiation hardened 16K CMOS PROM,
organized in a 2K word by 8-bit format. The chip is manufactured
using a radiation hardened CMOS process, and is designed to be
functionally equivalent to the HM-6617. Synchronous circuit design
techniques combine with CMOS processing to give this device high
speed performance with very low power dissipation.
On chip address latches are provided, allowing easy interfacing with
recent generation microprocessors that use multiplexed address/data
bus structure, such as the HS-80C85RH or HS-80C86RH. The output
enable control (G) simplifies microprocessor system interfacing by
allowing output data bus control, in addition to, the chip enable
control. Synchronous operation of the HS-6617RH is ideal for high
speed pipe-lined architecture systems and also in synchronous logic
replacement functions.
Applications for the HS-6617RH CMOS PROM include low power
microprocessor based instrumentation and communications systems,
remote data acquisition and processing systems, processor control
store, and synchronous logic replacement.
Pinouts
24 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T24
TOP VIEW
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
Q0 9
Q1 10
Q2 11
GND 12
24 VDD
23 A8
22 A9
21 P
20 G
19 A10
18 E
17 Q7
16 Q6
15 Q5
14 Q4
13 Q3
24 LEAD CERAMIC METAL SEAL FLATPACK
PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F24
TOP VIEW
A7 1
24 VDD
A6 2
23 A8
A5 3
22 A9
A4 4
21 P
A3 5
20 G
A2 6
19 A10
A1 7
18 E
A0 8
17 Q7
Q0 9
16 Q6
Q1 10 15 Q5
Q2 11 14 Q4
GND 12 13 Q3
Ordering Information
PART NUMBER
HS1-6617RH-Q
HS1-6617RH-8
HS1-6617RH/SAMPLE
HS1-6617RH/PROTO
HS9-6617RH-Q
HS9-6617RH-8
HS9-6617RH/Sample
HS9-6617RH/PROTO
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
25oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
25oC
-55oC to +125oC
PACKAGE
24 Lead SBDIP
24 Lead SBDIP
24 Lead SBDIP
24 Lead SBDIP
24 Lead Flatpack
24 Lead Flatpack
24 Lead Flatpack
24 Lead Flatpack
PIN DESCRIPTION
A Address Input
Q Data Output
E Chip Enable
G Output Enable
P Program Enable (P Hardwired to
VDD, except during programming)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518742
File Number 3033.3
1 page  
HS-6617RH
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC)
PARAMETER
SYMBOL
DELTA LIMITS
Standby Supply Current
IDDSB
±10µA
Input Leakage Current
IOZ
± 1µA
II ±100nA
Output Low Voltage
VOL
± 60mV
Output High Voltage
VOH
± 400mV
TABLE 6. APPLICABLE SUBGROUPS
GROUP A SUBGROUPS
CONFORMANCE
GROUP
MIL-STD-883
METHOD
TESTED FOR -Q
RECORDED
FOR -Q
TESTED FOR -8
RECORDED
FOR -8
Initial Test
100% 5004
1, 7, 9
1 (Note 2)
1, 7, 9
Interim Test
100% 5004
1, 7, 9, ∆
1, ∆ (Note 2)
1, 7, 9
PDA
100% 5004
1, 7, ∆
- 1, 7
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
- 2, 3, 8A, 8B, 10, 11
Group A (Note 1)
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
- 1, 2, 3, 7, 8A, 8B, 9,
10, 11
Subgroup B5
Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆ 1, 2, 3, ∆ (Note 2)
-
Subgroup B6
Sample 5005
1, 7, 9
--
Group C
Sample 5005
-
- 1, 2, 3, 7, 8A, 8B, 9,
10, 11
Group D
Sample 5005
1, 7, 9
- 1, 7, 9
Group E, Subgroup 2
Sample 5005
1, 7, 9
- 1, 7, 9
NOTES:
1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised.
2. Table 5 parameters only
Spec Number 518742
5
5 Page 
Semiconductor
HS-6617RH
DESIGN INFORMATION
July 1995
2K x 8 CMOS PROM
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as
application and design information only. No guarantee is implied.
Background Information HS-6617RH Programming
PROGRAMMING SPECIFICATIONS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Input "0"
VIL
0.0 0.2 0.8
V
Voltage "1"
VIH
VDD-2 VDD VDD+0.3
V
6
Programming VDD
VDDPROG
10.0 10.0 10.0
V
2
Operating VDD
VDD1
4.5 5.5 5.5
V
Special Verify
VDD2
4.0 - 6.0 V
3
Delay Time
td 1.0 1.0 - µs
Rise Time
tr 1.0 10.0 10.0 µs
Fall Time
tf 1.0 10.0 10.0 µs
Chip Enable Pulse Width
TEHEL
50 -
- ns
Address Valid to Chip Enable Low Time
TAVEL
20 -
- ns
Chip Enable Low to Output Valid Time
TELQV
- - 120 ns
Programming Pulse Width
tpw
90 100 110 µs
4
Input Leakage at VDD = VDDPROG
tIP
-10 +1.0 10
µA
Data Output Current at VDD = VDDPROG
IOP - -5.0 -10 mA
Output Pull-Up Resistor
Rn 5 10 15
Ambient Temperature
TA - 25
NOTES:
1. All inputs must track VDD (pin 24) within these limits.
2. VDDPROG must be capable of supplying 500mA. VDDPROG Power Supply tolerence ±3% (Max.)
3. See Steps 22 through 29 of the Programming Algorithm.
4. See Step 11 of the Programming Algorithm.
5. All outputs should be pulled up to VDD through a resistor of value Rn.
6. Except during programming (See Programming Cycle Waveforms).
-
kΩ
oC
5
Spec Number 518742
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HS9-6617RH-Q.PDF ] | |
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