PDF HS1-82C55ARH-8 Data sheet ( Hoja de datos )

Número de pieza	HS1-82C55ARH-8
Descripción	Radiation Hardened CMOS Programmable Peripheral Interface
Fabricantes	Intersil Corporation
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No Preview Available ! HS-82C55ARH September 1995 Radiation Hardened CMOS Programmable Peripheral Interface Features Pinout • Radiation Hardened - Total Dose >105 RAD (Si) - Transient Upset <108 RAD (Si)/s - Latch Up Free EPI-CMOS • Low Power Consumption - IDDSB = 20µA • Pin Compatible with NMOS 8255A and the Intersil 82C55A • High Speed, No “Wait State” Operation with 5MHz HS-80C86RH • 24 Programmable I/O Pins • Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up Resistors • Direct Bit Set/Reset Capability • Enhanced Control Word Read Capability • Hardened Field, Self-Aligned, Junction Isolated CMOS Process • Single 5V Supply • 2.0mA Drive Capability on All I/O Port Outputs • Military Temperature Range: -55oC to +125oC Description The Intersil HS-82C55ARH is a high performance, radiation hardened CMOS version of the industry standard 8255A and is manufactured using a hardened ﬁeld, self-aligned silicongate CMOS process. It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which are organized into two 8-bit and two 4-bit ports. Each port may be programmed to function as either an input or an output. Additionally, one of the 8-bit ports may be programmed for bi-directional operation,and the two 4-bit ports can be programmed to provide handshaking capabilities. The high performance, radiation hardness, and industry standard conﬁguration of the HS-82C55ARH make it compatible with the HS-80C86RH radiation hardened microprocessor. Static CMOS circuit design insures low operating power. Bus hold circuitry eliminates the need for pull-up resistors. The Intersil hardened ﬁeld CMOS process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T40 TOP VIEW PA3 PA2 PA1 PA0 RD CS GND A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 PA4 39 PA5 38 PA6 37 PA7 36 WR 35 RESET 34 D0 33 D1 32 D2 31 D3 30 D4 29 D5 28 D6 27 D7 26 VDD 25 PB7 24 PB6 23 PB5 22 PB4 21 PB3 Pin Description PIN D7 - D0 RESET CS RD WR DESCRIPTION Data Bus (Bi-Directional Reset Input Chip Select Read Input Write Input Ordering Information A0 - A1 Port Address PART NUMBER HS1-82C55ARH-Q HS1-82C55ARH-8 HS1-82C55ARH/Sample TEMPERATURE -55oC to +125oC -55oC to +125oC +25oC PACKAGE 40 Lead SBDIP 40 Lead SBDIP 40 Lead SBDIP PA7 - PA0 PB& - PB0 PC7 - PC0 VDD GND Port A (Bit) Port B (Bit) Port C (Bit) +5 volts 0 volts CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 970 Spec Number 518060 File Number 3191.1 1 page Speciﬁcations HS-82C55ARH TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS TA = -55oC to +125oC (Continued) PARAMETER SYMBOL CONDITIONS SUB- GROUPS TEMPERATURE LIMITS MIN MAX UNITS WR = 1 to OBF = 0 TWHOL VDD = 4.5, 5.5V 9, 10, 11 -55oC, +25oC, +125oC - 150 ns ACK = 0 to OBF = 1 TKLOH VDD = 4.5, 5.5V 9, 10, 11 -55oC, +25oC, +125oC - 150 ns STB = 0 to IBF = 1 TSLIH VDD = 4.5, 5.5V 9, 10, 11 -55oC, +25oC, +125oC - 150 ns RD = 1 to IBF = 0 TRHIL VDD = 4.5, 5.5V 9, 10, 11 -55oC, +25oC, +125oC - 150 ns RD = 0 to INTR = 1 TRLNL VDD = 4.5, 5.5V 9, 10, 11 -55oC, +25oC, +125oC - 200 ns STB = 1 t INTR = 1 TSHNH VDD = 4.5, 5.5V 9, 10, 11 -55oC, +25oC, +125oC - 150 ns ACK = 1 to INTR = 1 TKHNH VDD = 4.5, 5.5V 9, 10, 11 -55oC, +25oC, +125oC - 150 ns WR = 0 to INTR = 0 TWLNL VDD = 4.5, 5.5V 9, 10, 11 -55oC, +25oC, +125oC - 200 ns RESET Pulse Width TRSHRSL VDD = 4.5, 5.5V (Note 2) 9, 10, 11 -55oC, +25oC, +125oC 500 - ns NOTES: 1. AC’s tested at worst case VDD, guaranteed over full operating range. 2. Period of initial RESET pulse after power-on must be at least 50µs. Subsequenct RESET pulses may be 500ns minimum. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS TEMPERATURE MIN MAX UNITS Input Capacitance CIN VDD = Open, f = 1MHz, All measurements referenced to device ground TA = +25oC - 10 pF I/O Capacitance CI/O VDD = Open, f = 1MHz, All measurements referenced to device ground TA = +25oC - 20 pF Data Float After RD ACK = 1 to Output Float TRHDX TKHPZ VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V -55oC < TA < +125oC - 75 ns -55oC < TA < +125oC - 250 ns NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics TALBE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS See +25oC limits in Table 1 and Table 2 for Post RAD limits (Subgroups 1, 7, 9) Spec Number 518060 974 5 Page Irradiation Circuit HS-82C55ARH CMOS PROGRAMMABLE PERIPHERAL INTERFACE +5.5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 +5.5V 32 31 30 29 28 27 26 25 24 23 22 21 NOTE: 1. VDD = 5.5V Spec Number 518060 980 11 Page

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