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PDF HV5630DJ Data sheet ( Hoja de datos )
| Número de pieza | HV5630DJ | |
| Descripción | 32-Channel Serial To Parallel Converter | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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Supertex inc.
HV5630
32-Channel Serial to Parallel Converter
With Open Drain Outputs
Features
►► Processed with HVCMOS® technology
►► Sink current minimum 100mA
►► Shift register speed 8.0MHz
►► Polarity and Blanking inputs
►► CMOS compatible inputs
►► Forward and reverse shifting options
►► Diode to VPP allows efficient power recovery
General Description
The HV5630 is a low-voltage serial to high-voltage parallel
converter with open drain outputs. This device has been designed
for use as a driver for AC-electroluminescent displays. It can also
be used in any application requiring multiple output high voltage
current sinking capabilities such as driving inkjet and electrostatic
print heads, plasma panels, vacuum fluorescent, or large matrix
LCD displays.
This device consists of a 32-bit shift register, 32 latches, and control
logic to perform the polarity select and blanking of the outputs. Data
is shifted through the shift register on the high to low transition of the
clock. The HV5630 shifts in the clockwise direction when viewed
from the top of the package. A data output buffer is provided for
cascading devices. This output reflects the current status of the last
bit of the shift register. Operation of the shift register is not affected
by the LE (latch enable), BL (blanking), or the POL (polarity) inputs.
Transfer of data from the shift register to the latch occurs when the
LE (latch enable) input is high. The data in the latch is stored when
LE is low.
Functional Block Diagram
POL
BL
LE
DATA
IN
CLK
32-Bit
Shift
Register
DATA
OUT
Latch
Latch
Latch
Latch
HVOUT1
HVOUT2
(Outputs 3 to 30 not shown)
HVOUT31
HVOUT32
Doc.# DSFP-HV5630
C072313
Supertex inc.
www.supertex.com
1 page  
HV5630
44-Lead PLCC Pin Description
Pin
Function
Description
1 HVOUT17
2 HVOUT16
3 HVOUT15
4 HVOUT14
5 HVOUT13
6 HVOUT12
7 HVOUT11
8 HVOUT10
9
HVOUT9
High voltage outputs.
10 HVOUT8
11 HVOUT7
12 HVOUT6
13 HVOUT5
14 HVOUT4
15 HVOUT3
16 HVOUT2
17 HVOUT1
18
DATA OUT
Data output pin.
19 N/C
20 N/C No internal connection.
21 N/C
22
POL
Inverts the polarity of the HVOUT pins
23 CLK Clock pin, shift registers shift data on falling edge of input clock.
24
VSS
Reference voltage, usually ground.
25
VDD
Logic supply voltage.
26 LE Latch enable pin, data is shifted from shift register to latches on logic input high.
27
DATA IN
Data input pin.
28
BL
Blanking pin sets all HVout pins low or high depending upon state of polarity.
See function table.
29 N/C No internal connection.
30 HVOUT32
31 HVOUT31
32 HVOUT30
33 HVOUT29
34 HVOUT28
35 HVOUT27
36 HVOUT26
37
HVOUT25
High voltage outputs.
38 HVOUT24
39 HVOUT23
40 HVOUT22
41 HVOUT21
42 HVOUT20
43 HVOUT19
44 HVOUT18
Doc.# DSFP-HV5630
C072313
Supertex inc.
5 www.supertex.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet HV5630DJ.PDF ] | |
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