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PDF HV3418PG Data sheet ( Hoja de datos )
| Número de pieza | HV3418PG | |
| Descripción | 64-Channel Serial to Parallel Converter | |
| Fabricantes | Supertex Inc | |
| Logotipo |  |
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Supertex inc.
HV3418
64-Channel Serial to Parallel Converter
With High Voltage
Push-Pull Outputs
Features
►►Processed with HVCMOS® technology
►►Output voltages to 180V
►►Low power level shifting
►►Shift register speed:
6.0MHz @ VDD = 5.0V
12MHz @ VDD = 12V
►►Latched data outputs
►►Output polarity and blanking
►►CMOS compatible inputs
►►Forward and reverse shifting options
General Description
The HV3418 is a low voltage serial to high voltage parallel
converter with push-pull outputs. This device has been designed
for use as a printer driver for inkjet applications. It can also be
used in any application requiring multiple output, high voltage,
low current sourcing and sinking capabilities.
The device consists of a 64-bit shift register, 64 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through
the device. With DIR grounded, DIOA is Data-In and DIOB is
Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR
is at logic high, DIOB is Data-In and DIOA is Data-Out: data is
then shifted from HVOUT1 to HVOUT64. Data is shifted through
the shift register on the low to high transition of the clock. Data
output buffers are provided for cascading devices. Operation
of the shift register is not affected by the LE (latch enable), BL
(blanking), or the POL(polarity) inputs. Transfer of data from the
shift register to the latch occurs when the LE (latch enable) is
high. The data in the latch is stored during LE transition from
high to low.
Functional Block Diagram
POL
BL
LE
DIOA
CLK
64 bit
DIR
Static Shift
Register
64 Latches
DIOB
VPP
HVOUT1
HVOUT2
•
•
•
60 Additional
Outputs
•
•
•
HVOUT63
HVOUT64
Doc.# DSFP-HV3418
C071813
Supertex inc.
www.supertex.com
1 page  
HV3418
Function Table
Inputs
Outputs
Function
Data CLK LE BL POL DIR
Shift Reg
1 2...64
HV Outputs
1 2...64
Data Out
*
All on X X X L L X * *...*
All off X X X L H X * *...*
Invert mode
X
X LHLX
*
*...*
Load S/R H or L ↑
L H H X H or L *...*
Load/store
X
X ↓ HHX
*
*...*
data in latches X
X ↓HLX
*
*...*
Transparent
L
↑ HHHX
L
*...*
latch mode
H
↑ HHHX
H
*...*
I/O relation
DIOA
DIOB
↑
↑
XXX L
XXXH
QN→
QN→
QN+1
QN+1
Notes:
H = high level, L = low level = 0V, X = irrelevant, ↑ = low-to-high transition, ↓ = high-to-low transition.
* = dependent on previous stage’s state before the last CLK or last LE high.
H H...H
L L...L
* *...*
* *...*
* *...*
* *...*
L *...*
H *...*
-
-
*
*
*
*
*
*
*
*
DIOB
DIOA
Doc.# DSFP-HV3418
C071813
Supertex inc.
5 www.supertex.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HV3418PG.PDF ] | |
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