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PDF HT95A100 Data sheet ( Hoja de datos )
| Número de pieza | HT95A100 | |
| Descripción | I/O Type Phone 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor Inc | |
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HT95AXXX
I/O Type Phone 8-Bit MCU
Features
· Provide MASK type and OTP type version
· Operating voltage range: 2.4V~5.5V
· Program ROM
- HT95A400/40P: 16K´16 bits
- HT95A300/30P: 8K´16 bits
- HT95A200/20P: 4K´16 bits
- HT95A100/10P: 4K´16 bits
· Data RAM
- HT95A400/40P: 2880´8 bits
- HT95A300/30P: 2112´8 bits
- HT95A200/20P: 1152´8 bits
- HT95A100/10P: 384´8 bits
· Bidirectional I/O lines
- HT95A400/40P: 44 I/O lines
- HT95A300/30P: 28 I/O lines
- HT95A200/20P: 28 I/O lines
- HT95A100/10P: 20 I/O lines
· 16-bit table read instructions
· Subroutine nesting
- HT95A400/40P: 12 levels
- HT95A300/30P: 8 levels
- HT95A200/20P: 8 levels
- HT95A100/10P: 4 levels
· Timer
- Two 16-bit programmable Timer/Event Counter
- Real time clock (RTC)
- Watchdog Timer (WDT)
· Programmable frequency divider (PFD)
Supported for HT95A400/40P, HT95A300/30P,
HT95A200/20P
· Dual system clock: 32768Hz, 3.58MHz
· Four operating modes: Idle mode, Sleep mode,
Green mode and Normal mode
· Up to 1.117ms instruction cycle with 3.58MHz system
clock
· All instructions in one or two machine cycles
· Built-in 3.58MHz DTMF Generator
· Built-in dialer I/O
· HT95A400/40P: 64-pin QFP package
HT95A300/40P: 48-pin SSOP package
HT95A200/20P: 48-pin SSOP package
HT95A100/10P: 28-pin SOP package
Applications
· Cordless Phone
· Fax and answering machines
· Other communication system
General Description
The HT95AXXX family MCU are 8-bit high performance
RISC-like microcontrollers with built-in DTMF generator
and dialer I/O which provide MCU dialer implementation
or system control features for telecom product applica-
tions. The phone controller has a built-in program ROM,
data RAM and I/O lines for high end products design. In
addition, for power management purpose, it has a
built-in frequency up conversion circuit (32768Hz to
3.58MHz) which provides dual system clock and four
types of operation modes. For example, it can operate
with low speed system clock rate of 32768Hz in green
mode with little power consumption. It can also operate
with high speed system clock rate of 3.58MHz in normal
mode for high performance operation. To ensure
smooth dialer function and to avoid MCU shut-down in
extreme low voltage situation, the dialer I/O circuit is
built-in to generate hardware dialer signals such as
on-hook, hold-line and hand-free. Built-in real time clock
and programmable frequency divider are provided for
additional fancy features in product developments. The
device is best suited for phone products that comply
with versatile dialer specification requirements of differ-
ent areas or countries.
Rev. 1.20
1 May 26, 2004
1 page  
HT95AXXX
Electrical Characteristics
Ta=25°C
Symbol
Parameter
CPU
IIDL
Idle Mode Current
ISLP Sleep Mode Current
IGRN
Green Mode Current
INOR
Normal Mode Current
VIL I/O Port Input Low Voltage
VIH I/O Port Input High Voltage
IOL I/O Port Sink Current
IOH I/O Port Source Current
RPH Pull-high Resistor
Dialer I/O
IXMO
XMUTE Leakage Current
IOLXM
XMUTE Sink Current
IHKS HKS Input Current
RHFI
HFI Pull-low Resistance
RHDI
HDI Pull-high Resistance
IOH2 HFO Source Current
IOL2 HFO Sink Current
IOH3 HDO Source Current
IOL3 HDO Sink Current
IOH4 PO Source Current
IOL4 PO Sink Current
IOL5 DNPO Sink Current
DTMF Generator
VTDC
DTMF Output DC Level
VTOL
DTMF Sink Current
VTAC
DTMF Output AC Level
RL DTMF Output Load
ACR Column Pre-emphasis
THD
Tone Signal Distortion
Test Conditions
VDD Conditions
Min. Typ. Max. Unit
5V
32768Hz off, 3.58MHz off,
CPU off, WDT off, no load
5V
32768Hz on, 3.58MHz off,
CPU off, WDT off, no load
5V
32768Hz on, 3.58MHz off,
CPU on, WDT off, no load
32768Hz on, 3.58MHz on,
5V CPU on, WDT on,
DTMF generator off, no load
5V ¾
5V ¾
5V ¾
5V ¾
5V ¾
¾
¾
¾
¾
0
4
4
-2
10
¾2
¾ 30
¾ 50
¾3
¾1
¾5
6¾
-3 ¾
30 ¾
mA
mA
mA
mA
V
V
mA
mA
kW
2.5V XMUTE pin=2.5V
2.5V XMUTE pin=0.5V
2.5V HKS pin=2.5V
2.5V VHFI=2.5V
2.5V VHDI=0V
2.5V VOH=2V
2.5V VOL=0.5V
2.5V VOH=2V
2.5V VOL=0.5V
2.5V VOH=2V
2.5V VOL=0.5V
2.5V VOL=0.5V
¾¾1
mA
1
¾¾
mA
¾
¾ 0.1
mA
¾ 200 ¾
kW
¾ 200 ¾
kW
-1 ¾ ¾ mA
1
¾¾
mA
-1 ¾ ¾ mA
1
¾¾
mA
-1 ¾ ¾ mA
1
¾¾
mA
1
¾¾
mA
¾¾
¾ VDTMF=0.5V
¾ Row group, RL=5kW
¾ THD£-23dB
¾ Row group=0dB
¾ RL=5kW
0.45VDD ¾ 0.7VDD V
0.1 ¾ ¾ mA
120 155 180 mVrms
5
¾¾
kW
1 2 3 dB
¾ -30 -23 dB
Rev. 1.20
5 May 26, 2004
5 Page 
HT95AXXX
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] will access the memory
pointed to by MP0 and MP1, respectively. Reading loca-
tion [00H] or [02H] indirectly returns the result 00H,
while writing it leads to no operation. MP0 is indirectly
addressable in bank0, but MP1 is available for all banks
by switch BP [04H]. If BP is unequal to 00H, the indirect
addressing mode to read/write operation from 00H~3FH
will return the result as same as the value of bank0.
The memory pointer registers MP0 and MP1 are 8-bits
registers, and the bank pointer register BP is 6-bits reg-
ister for the HT95A400/40P or 5-bits for the other de-
vices in the series.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can operate with immediate data. All data movement
between two data memory locations must pass through
the accumulator.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This status register contains the carry flag (C), auxiliary
carry flag (AC), zero flag (Z), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO). It
also records the status information and controls the op-
eration sequence.
Except for the TO and PDF flags, bits in the status regis-
ter can be altered by instructions, similar to the other
registers. Data written into the status register will not
change the TO or PDF flag. Operations related to the
status register may yield different results from those in-
tended. The TO flag can be affected only by system
power-up, a WDT time-out or executing the ²CLR WDT²
or ²HALT² instruction. The PDF flag can be affected only
by executing the ²HALT² or ²CLR WDT² instruction or
during a system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automati-
cally pushed onto the stack.
If the contents of the status are important and if the sub-
routine can corrupt the status register, precautions must
be taken to save it .
Interrupt
The telephone controller provides an external interrupt,
internal timer/event counter interrupt, an internal real
time clock interrupt and internal dialer I/O interrupt. The
Interrupt Control Registers 0 and Interrupt Control Reg-
ister 1 both contains the interrupt control bits that set the
enable/disable and the interrupt request flags
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by hardware clearing the EMI
bit). This scheme may prevent any further interrupt nest-
ing. Other interrupt requests may occur during this inter-
val but only the interrupt request flag is recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 (INTC1) may be set to allow interrupt nesting.
Register
STATUS
(0AH)
Label
C
AC
Z
OV
PDF
TO
¾
Bits Function
C is set if the operation results in a carry during an addition operation or if a borrow
0 does not take place during a subtraction operation; otherwise C is cleared. Also it is
affected by a rotate through carry instruction.
1
AC is set if the operation results in a carry out of the low nibbles in addition or no bor-
row from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2 Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.
3
OV is set if the operation results in a carry into the highest-order bit but not a carry
out of the highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF is cleared when either a system power-up or executing the CLR WDT instruc-
tion. PDF is set by executing the HALT instruction.
5
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction.
TO is set by a WDT time-out.
6, 7 Unused bit, read as ²0²
Rev. 1.20
11 May 26, 2004
11 Page | ||
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| PDF Descargar | [ Datasheet HT95A100.PDF ] | |
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