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PDF HT82V14 Data sheet ( Hoja de datos )
| Número de pieza | HT82V14 | |
| Descripción | 14-Bit CCD/CIS Analog Signal Processor | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT82V14
14-Bit CCD/CIS Analog Signal Processor
Features
· Low power CMOS : 350 mW
· 9 ADC clock latency for digital data output
· 14-bit 6 MSPS A/D converter
· 3-channel correlated double sampler
· 1~6 programmable gain
· Input clamp circuitry for CDS-mode
· Internal/external circuitfor CIS
General Description
The HT82V14 is a complete analog signal pro-
cessor for CCD imaging applications. It fea-
tures a 3-channel architecture designed to
sample and condition the outputs of the
trilinear color CCD arrays. Each channel con-
sists of an input clamp, Correlated Double
Sampler (CDS), offset DAC and Programmable
Gain Amplifier (PGA), multiplexed to a high
performance 14-bit A/D converter.
Block Diagram
O FFSET R EFT C M L R EF
· Internal/external voltage reference
· Internal MUX for channel operation
· 1 or 3-channel operation
· Pixel-rate or line-rate switch operation
· Programmable 3-wire serial interface
· +5V digital I/O compatibility
· 28-pin SOP/SOJ package
The CDS amplifiers may be disabled for use
with sensors such as Contact Image Sensors
(CIS) and CMOS active pixel sensors, which do
not require CDS.
The 14-bit digital output is multiplexed into an
8-bit output word that is accessed using two
read cycles. The internal registers are pro-
grammed through a 3-wire serial interface,
which provides gain, offset, and operating mode
adjustments.
OE
V o lta g e R e fe r e n c e
R IN C L P C D S +
VG A
P ix e l R a te
G u a ra n te e
G IN
C LP C D S
+
VG A
M UX PG A
1 4 - b it
ADC
D 13~D 0
B IN C L P C D S
+ VG A
C o n tro l
P o rt
S C LK
CS
SD ATA
3 ´ 8 b its
DAC
O ffs e t
3 ´ 2 b its
C o a rs e
G a in
C o n fig
R e g is te r
3 ´ 5 b its
F in e
G a in
C D S C LK 1 C D S C LK 2
A D C C LK
1 July 12, 2000
1 page  
HT82V14
Timing Diagrams
Timing Mode
A
B
C
D
Sensor Mode
CDS
CDS
CIS/SHA
CIS/SHA
Channel Mode
3-channel internally-defined and pixel-rate mux (00)
1-channel internally-defined mux (01)
3-channel internally-defined and pixel-rate mux (00)
1-channel internally-defined mux (01)
Mode A
A n a lo g In p u t
C D S C LK 1
C D S C LK 2
A D C C LK
D 13~D 0
P ix e l n
tA D
tC 1 A tC 1 C 2 A
tA D
tC 2 C 1 A
tC 2 A
P ix e l n + 1
tC R A
tN V P
tS T L 1
tN V P
RG B RG B R
tC P
R (n -4 )
D 13~D 6
R (n -4 )
D 5~D 0
G (n -4 )
D 13~D 6
G (n -4 )
D 5~D 0
B (n -4 )
D 13~D 6
B (n -4 )
D 5~D 0
R (n -3 )
D 13~D 6
R (n -3 )
D 5~D 0
G (n -3 )
D 13~D 6
G (n -3 )
D 5~D 0
B (n -3 )
D 13~D 6
B (n -3 )
D 5~D 0
R (n -2 )
D 13~D 6
R (n -2 )
D 5~D 0
G
B
Note: DATA timing from pixel to pixel is decided by the first rising edge of ADCCLK when
CDSCLK2 is from high to low.
Mode B
A n a lo g In p u t
C D S C LK 1
P ix e l n
tA D
tC 1 B tC 1 C 2 B
tA D
tC 2 C 1 B
P ix e l n + 1
tC R B
P ix e l n + 2
tC 2 B
C D S C LK 2
D 13~D 0
D (n -1 0 )
D 13~D 6
D (n -1 0 )
D 5~D 0
D (n -9 )
D 13~D 6
D (n -9 )
D 5~D 0
D (n -8 )
D 13~D 6
5 July 12, 2000
5 Page 
· Truth table for 1 channel index mode
Bit1
Bit0
0 0 R channel
0 1 G channel
1 0 B channel
1 1 Reserved
· Truth table for 3 channel index mode
Bit4
Bit3
Bit2
0 0 0 R®G®B
0 0 1 R®B®G
0 1 0 G®R®B
0 1 1 G®B®R
1 0 0 B®R®G
1 0 1 B®G®R
1 1 0 Reserved
1 1 1 Reserved
Application Circuits
HT82V14
0 .1 m F
1 C D S C LK 1
2 C D S C LK 2
3 A D C C LK
4 OE
5 DRVDD
6 DRVSS
7 D 1 3 /D 5
8 D 1 2 /D 4
9 D 1 1 /D 3
1 0 D 1 0 /D 2
1 1 D 9 /D 1
1 2 D 8 /D 0
13 D 7
14 D 6
AVDD
AVSS
R IN
O FFSET
G IN
CM L
B IN
R EFT
REF
AVSS
AVDD
S LO A D
S C LK
SD ATA
2 8 0 .1 m F
27
2 6 0 .1 m F
25
24
2 3 0 .1 m F
0 .1 m F
2 2 0 .1 m F
21
20
1 9 1 0 m F 0 .1 m F
18
1 7 0 .1 m F
16
15
0 .1 m F
0 .1 m F
H T82V 14
Note: Decoupling capacitor of RIN, GIN, BIN may change its value from 300pF to 0.1mF depending
on the system environment.
11 July 12, 2000
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HT82V14.PDF ] | |
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