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PDF HT82K96E Data sheet ( Hoja de datos )
| Número de pieza | HT82K96E | |
| Descripción | 8-Bit USB Multimedia Keyboard Encoder OTP MCU | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT82K96E
8-Bit USB Multimedia Keyboard Encoder OTP MCU
Features
· Operating voltage:
fSYS=6M/12MHz: 4.4V~5.5V
· Low voltage reset function
· 32 bidirectional I/O lines (max.)
· 8-bit programmable timer/event counter with over-
flow interrupt
· 16-bit programmable timer/event counter and over-
flow interrupts
· Crystal oscillator (6MHz or 12MHz)
· Watchdog Timer
· 6 channels 8-bit A/D converter
· PS2 and USB modes supported
· USB1.1 low speed function
· 4 endpoints supported (endpoint 0 included)
· 4096´15 program memory ROM
· 160´8 data memory RAM
· HALT function and wake-up feature reduce power
consumption
· 8-level subroutine nesting
· Up to 0.33ms instruction cycle with 12MHz system
clock at VDD=5V
· Bit manipulation instruction
· 15-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· 20-pin SOP, 48-pin SSOP package
General Description
This device is an 8-bit high performance RISC-like
microcontroller designed for USB product applications.
It is particularly suitable for use in products such as
mice, keyboards and joystick. A HALT feature is in-
cluded to reduce power consumption.
Rev. 1.70
1 April 22, 2004
1 page  
HT82K96E
Symbol
Parameter
Test Conditions
VDD Conditions
IOL4 I/O Port Sink Current for PC0
5V VOL=0.4V
IOH1 I/O Port Source Current for PC0
5V VOH=3.4V
IOH2
I/O Port Source Current for PA, PB,
PC1~PC7, PD
5V
VOH=3.4V
RPH Pull-high Resistance for PA, PB, PC, PD 5V
¾
RPL Pull-low Resistance for PA1~PA5
5V
¾
VLVR
Low Voltage Reset
¾¾
VV33O
EA/D
3.3V Regulator Output
A/D Conversion Error
5V IV33O=-5mA
5V Total error
Min. Typ. Max. Unit
10 25
-8 -16
¾
¾
mA
mA
-2 -5 ¾ mA
25 50 80 kW
15 30 45 kW
3 3.4 4.0
V
3.0 3.3 3.6
V
¾1
2 LSB
A.C. Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD Conditions
Min. Typ. Max. Unit
fSYS System Clock (Crystal OSC)
5V ¾
6 ¾ 12 MHz
fTIMER Timer I/P Frequency (TMR0/TMR1)
5V
¾
0 ¾ 12 MHz
tWDTOSC Watchdog Oscillator
5V ¾
15 31 70
ms
tWDT1
tWDT2
Watchdog Time-out Period (WDT OSC) 5V Without WDT prescaler 4 8 16
Watchdog Time-out Period (System Clock) ¾ Without WDT prescaler ¾ 1024 ¾
ms
tSYS
tRES External Reset Low Pulse Width ¾ ¾
1 ¾¾
ms
tSST System Start-up Timer Period
Wake-up from HALT
¾ Power-up, Watchdog
Time-out from normal
¾ 1024 ¾
tSYS
¾ 1024 ¾ tWDTOSC
tINT Interrupt Pulse Width
¾¾
1 ¾¾
ms
tADC A/D Conversion Time
¾¾
¾ 64 ¾
tA/D
1
Note: tA/D=fA/D , fA/D=A/D clock source frequencies (6MHz, 3MHz, 1.5MHz, 0.75MHz)
Rev. 1.70
5 April 22, 2004
5 Page 
HT82K96E
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the ²RETI² in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No. Interrupt Source Priority Vector
a USB interrupt
1 04H
b Timer/Event Counter 0 overflow 2 08H
c Timer/Event Counter 1 overflow 3 0CH
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), USB interrupt request flag (USBF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en-
able USB interrupt bit (EUI) and enable master interrupt
bit (EMI) constitute an interrupt control register (INTC)
which is located at 0BH in the data memory. EMI, EUI,
ET0I and ET1I are used to control the enabling/dis-
abling of interrupts. These bits prevent the requested in-
terrupt from being serviced. Once the interrupt request
flags (T0F, T1F, USBF) are set, they will remain in the
INTC register until the interrupts are serviced or cleared
by a software instruction.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the ²CALL² operates in the interrupt subrou-
tine.
Oscillator Configuration
There is an oscillator circuits in the microcontroller.
O SC1
O SC2
C r y s ta l O s c illa to r
System Oscillator
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. In stead of
a crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 31ms. The WDT oscillator can
be disabled by ROM code option to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (sys-
tem clock divided by 4), determines the ROM code op-
tion. This timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by ROM code option. If the
Watchdog Timer is disabled, all the executions related
to the WDT result in no operation.
S y s te m C lo c k /4
W DT
O SC
ROM
C ode
O p tio n
S e le c t
8 - b it C o u n te r
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
W S 0~W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.70
11 April 22, 2004
11 Page | ||
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| PDF Descargar | [ Datasheet HT82K96E.PDF ] | |
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