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PDF HT46R47 Data sheet ( Hoja de datos )
| Número de pieza | HT46R47 | |
| Descripción | 8-Bit OTP Battery Charger Controller | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT46R47
8-Bit OTP Battery Charger Controller
Features
· Operating voltage:
fSYS=4MHz: 3.3V~5.5V
fSYS=8MHz: 4.5V~5.5V
· 13 bidirectional I/O lines (max.)
· 1 interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with
overflow interrupt and 7-stage prescaler
· On-chip crystal and RC oscillator
· Watchdog Timer
· 2048´14 program memory PROM
· 64´8 data memory RAM
· Supports PFD for sound generation
· HALT function and wake-up feature reduce
power consumption
General Description
The device is an 8-bit high performance
RISC-like microcontroller designed for multi-
ple I/O product applications. The device is par-
ticularly suitable for use in products such as
battery charger controllers and A/D applica-
tions. A HALT feature is included to reduce
power consumption.
· Up to 0.5ms instruction cycle with 8MHz
system clock at VDD=5V
· Six-level subroutine nesting
· 4 channels 9-bit resolution (8-bit accuracy)
A/D converter
· 1 channel (6+2)-bit PWM output shared
with an I/O line
· Bit manipulation instruction
· 14-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine
cycles
· Low voltage reset function
· 18-pin DIP/SOP package
The program and option memories can be elec-
trically programmed, making the microcontrol-
ler suitable for use in product development.
Rev. 1.40
1 July 18, 2001
1 page  
HT46R47
Symbol
Parameter
RPH Pull-high Resistance
EAD A/D Conversion Error
Test Conditions
VDD
3.3V
Conditions
¾
5V ¾
5V ¾
Min. Typ. Max. Unit
40 60 80 kW
10 30 50 kW
¾ ±0.5 ±1 LSB
A.C. Characteristics
Ta=25°C
Symbol
Parameter
fSYS1
System Clock
(Crystal OSC)
Test Conditions
VDD
3.3V
Conditions
¾
5V ¾
Min. Typ. Max. Unit
400 ¾ 4000 kHz
400 ¾ 8000 kHz
fSYS2
System Clock (RC OSC)
3.3V
5V
¾
¾
400 ¾ 4000 kHz
400 ¾ 8000 kHz
fTIMER
3.3V
Timer I/P Frequency (TMR)
5V
¾
¾
0 ¾ 4000 kHz
0 ¾ 8000 kHz
tAD
tADC
A/D Clock Period
A/D Conversion Time
tWDTOSC Watchdog Oscillator
5V
¾
3.3V
5V
¾
¾
¾
¾
1 ¾ ¾ ms
¾ 76 ¾ tAD
43 86 168 ms
36 72 144 ms
tWDT1
Watchdog Time-out Period 3.3V
(RC)
5V
¾
2.8 5.6 11
2.3 4.7 9.4
s
s
tWDT2
Watchdog Time-out Period
(System Clock)
¾
¾ 217 ¾ 218 tSYS
tRES
External Reset Low Pulse
Width
¾
¾
1 ¾ ¾ ms
tSST
System Start-up Timer
Period
¾ Wake-up from HALT ¾ 1024 ¾ *tSYS
tINT Interrupt Pulse Width
¾
¾
1 ¾ ¾ ms
Note: *tSYS=1/fSYS
Rev. 1.40
5 July 18, 2001
5 Page 
HT46R47
sired control sequence, the contents should be
saved in advance.
External interrupts are triggered by a high to
low transition of INT and the related interrupt
request flag (EIF; bit 4 of INTC) will be set.
When the interrupt is enabled, the stack is not
full and the external interrupt is active, a sub-
routine call to location 04H will occur. The in-
terrupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
The internal timer/event counter interrupt is
initialized by setting the timer/event counter
interrupt request flag (TF; bit 5 of INTC),
caused by a timer overflow. When the interrupt
is enabled, the stack is not full and the TF bit is
set, a subroutine call to location 08H will occur.
The related interrupt request flag (TF) will be
reset and the EMI bit cleared to disable further
interrupts.
The A/D converter interrupt is initialized by
setting the A/D converter request flag (ADF; bit
6 of INTC), caused by an end of A/D conversion.
When the interrupt is enabled, the stack is not
full and the ADF is set, a subroutine call to loca-
tion 0CH will occur. The related interrupt re-
quest flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
During the execution of an interrupt subroutine,
other interrupt acknowledgments are held until
the "RETI" instruction is executed or the EMI
bit and the related interrupt control bit are set to
1 (of course, if the stack is not full). To return
from the interrupt subroutine, "RET" or "RETI"
may be invoked. RETI will set the EMI bit to en-
able an interrupt service, but RET will not.
Interrupts, occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are en-
abled. In the case of simultaneous requests the
following table shows the priority that is ap-
plied. These can be masked by resetting the
EMI bit.
No. Interrupt Source Priority Vector
a External Interrupt
1
04H
b
Timer/event
Counter Overflow
2
08H
c
A/D Converter
Interrupt
3 0CH
The timer/event counter interrupt request flag
(TF), external interrupt request flag (EIF), A/D
Register Bit No. Label
Function
0
EMI
Controls the master (global) interrupt
(1= enabled; 0= disabled)
1
EEI
Controls the external interrupt
(1= enabled; 0= disabled)
2
ETI
Controls the timer/event counter interrupt
(1= enabled; 0= disabled)
INTC
3
EADI
Controls the A/D converter interrupt
(1= enabled; 0= disabled)
(0BH)
4
EIF
External interrupt request flag
(1= active; 0= inactive)
5
TF
Internal timer/event counter request flag
(1= active; 0= inactive)
6
ADF
A/D converter request flag
(1= active; 0= inactive)
7 ¾ Unused bit, read as "0"
INTC register
Rev. 1.40
11 July 18, 2001
11 Page | ||
| Páginas | Total 45 Páginas | |
| PDF Descargar | [ Datasheet HT46R47.PDF ] | |
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