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PDF HT27C512 Data sheet ( Hoja de datos )
| Número de pieza | HT27C512 | |
| Descripción | CMOS 64K x 8-Bit OTP EPROM | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT27C512
CMOS 64K´8-Bit OTP EPROM
Features
· Operating voltage: +5.0V
· Programming voltage
- VPP=12.2V±0.2V
- VCC=5.8V±0.2V
· High-reliability CMOS technology
· Latch-up immunity to 100mA from -1.0V to
VCC+1.0V
· CMOS and TTL compatible I/O
· Low power consumption
- Active: 30mA max.
- Standby: 1mA typ.
· 64K´8-bit organization
· Fast read access time: 70ns
· Fast programming algorithm
· Programming time 75ms typ.
· Two line control (OE & CE)
· Standard product identification code
· Commercial temperature range (0°C to +70°C)
· 28-pin DIP/SOP, 32-pin PLCC package
General Description
The HT27C512 chip family is a low-power, 512K bit, +5V
electrically one-time programmable (OTP) read-only
memories (EPROM). Organized into 64K words with 8
bits per word, it features a fast single address location
programming, typically at 75ms per byte. Any byte can
be accessed in less than 70ns with respect to Spec. This
Block Diagram
eliminates the need for WAIT states in
high-performance microprocessor systems. The
HT27C512 has separate Output Enable (OE) and Chip
Enable (CE) controls which eliminate bus contention is-
sues.
R ow
A d d re s s
C o lu m n
A d d re s s
CE
O E /V P P
X -D e c o d e r
Y -D e c o d e r
CE & OE &
PG M & TEST
C o n tr o l L o g ic
C e ll A r r a y
Y - G a tin g
SA CKT
&
O u tp u t B u ffe r
VCC
VSS
D Q 0~D Q 7
Rev. 1.40
1 December 8, 2003
1 page  
HT27C512
Functional Description
Programming of the HT27C512
When the HT27C512 is delivered, the chip has all 512K
bits in the ²ONE² or HIGH state. ²ZEROs² are loaded
into the HT27C512 through the procedure of program-
ming.
The programming mode is entered when 12.2±0.2V is
applied to the OE/VPP pin and CE is at VIL. For pro-
gramming, the data to be programmed is applied with 8
bits in parallel to the data pins.
The programming flowchart in Figure 3. shows the fast
interactive programming algorithm. The interactive al-
gorithm reduces programming time by using 30ms to
105ms programming pulses and giving each address
only as many pulses as is necessary in order to reliably
program the data. After each pulse is applied to a given
address, the data in that address is verified. If the data is
not verified, additional pulses are given until it is verified
or until the maximum number of pulses is reached. This
process is repeated while sequencing through each ad-
dress of the HT27C512. This part of the programming
algorithm is carried at VCC=5.8V to assure that each
EPROM bit is programmed to a sufficiently high thresh-
old voltage. This ensures that all bits have sufficient
margin. After the final address is completed, the entire
EPROM memory is read at VCC=VPP=5.25±0.25V to verify
the entire memory.
Program Inhibit Mode
Programming of multiple HT27C512 in parallel with dif-
ferent data is also easily accomplished by using the Pro-
gram Inhibit Mode. Except for CE, all like inputs of the
parallel HT27C512 may be common. A TTL low-level
program pulse applied to an HT27C512 CE input with
OE/VPP=12.2±0.2V will program that HT27C512. A
high-level CE input inhibits the other HT27C512 from
being programmed.
Program Verify Mode
Verification should be performed on the programmed
bits to determine whether they were correctly pro-
grammed. The verification should be performed with
OE/VPP and CE at VIL. Data should be verified at tDV af-
ter the falling edge of CE.
Auto Product Identification
The Auto Product Identification mode allows the reading
out of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for use by
the programming equipment for the purpose of automat-
ically matching the device to be programmed with its
corresponding programming algorithm. This mode is
functional in the 25°C±5°C ambient temperature range
that is required when programming the HT27C512.
To activate this mode, the programming equipment
must force 12.0±0.5V on the address line A9 of the
HT27C512. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from VIL to VIH, when A1=VIH. All other address
lines must be held at VIH during Auto Product Identifica-
tion mode.
Byte 0 (A0=VIL) represents the manufacturer code, and
byte 1 (A0=VIH), the device code. For HT27C512, these
two identifier bytes are shown in the Operation mode
truth table. All identifiers for the manufacturer and de-
vice codes will possess odd parity, with the MSB (DQ7)
defined as the parity bit. When A1=VIL, the HT27C512
will read out the binary code of 7F, continuation code, to
signify the unavailability of manufacturer ID codes.
Read Mode
The HT27C512 has two control functions, both of which
must be logically satisfied in order to obtain data at out-
puts. Chip Enable (CE) is the power control and should
be used for device selection. Output Enable (OE) is the
output control and should be used to gate data to the
output pins, independent of device selection. Assuming
that addresses are stable, address access time () is
equal to the delay from CE to output (tCE). Data is avail-
able at the outputs (tOE) after the falling edge of OE, as-
suming the CE has been LOW and addresses have
been stable for at least tACC-tOE.
Standby Mode
The HT27C512 has CMOS standby mode which re-
duces the maximum VCC current to 10mA. It is placed in
CMOS standby when CE is at VCC±0.3V. The
HT27C512 also has a TTL-standby mode which re-
duces the maximum VCC current to 1.0mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state, inde-
pendent of the OE input.
Two-line Output Control Function
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
· Low memory power consumption
· Assurance that output bus contention will not occur.
It is recommended that CE be decoded and used as the
primary device-selection function, while OE be made a
common connection to all devices in the array and con-
nected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
Rev. 1.40
5 December 8, 2003
5 Page 
Product Tape and Reel Specifications
Reel Dimensions
T2
D
HT27C512
AB
C
T1
SOP 28W (300mil)
Symbol
Description
A Reel Outer Diameter
B Reel Inner Diameter
C Spindle Hole Diameter
D Key Slit Width
T1 Space Between Flange
T2 Reel Thickness
PLCC 32
Symbol
A
B
C
D
T1
T2
Description
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
Space Between Flange
Reel Thickness
Rev. 1.40
11
Dimensions in mm
330±1.0
62±1.5
13.0+0.5
-0.2
2.0±0.5
24.8+0.3
-0.2
30.2±0.2
Dimensions in mm
330±1.0
62±1.5
13.0+0.5
-0.2
2.0±0.5
24.8+0.3
-0.2
30.2±0.2
December 8, 2003
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HT27C512.PDF ] | |
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