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PDF HT27C010 Data sheet ( Hoja de datos )
| Número de pieza | HT27C010 | |
| Descripción | OTP CMOS 128Kx 8-Bit EPROM | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HT27C010 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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HT27C010
CMOS 128K´8-Bit OTP EPROM
Features
· Operating voltage: +5.0V
· Programming voltage
- VPP=12.5V±0.2V
- VCC=6.0V±0.2V
· High-reliability CMOS technology
· Latch-up immunity to 100mA from -1.0V to
VCC+1.0V
· CMOS and TTL compatible I/O
· Low power consumption
- Active: 30mA max.
- Standby: 1mA typ.
· 128K´8-bit organization
· Fast read access time: 70ns
· Fast programming algorithm
· Programming time 75ms typ.
· Two line controls (OE and CE)
· Standard product identification code
· Commercial temperature range (0°C to +70°C)
· 32-pin DIP/SOP/PLCC package
General Description
The HT27C010 chip family is a low-power, 1024K
(1,048,576) bit, +5V electrically one-time programmable
(OTP) read-only memories (EPROM). Organized into
128K words with 8 bits per word, it features a fast single
address location programming, typically at 75ms per
byte. Any byte can be accessed in less than 70ns with
Block Diagram
respect to Spec. This eliminates the need for WAIT
states in high-performance microprocessor systems.
The HT27C010 has separate Output Enable (OE) and
Chip Enable (CE) controls which eliminate bus conten-
tion issues.
R ow
A d d re s s
C o lu m n
A d d re s s
CE
OE
PG M
X -D e c o d e r
Y -D e c o d e r
CE & OE &
PG M & TEST
C o n tr o l L o g ic
C e ll A r r a y
Y - G a tin g
SA CKT
&
O u tp u t B u ffe r
VCC
VSS
VPP
D Q 0~D Q 7
Rev. 1.10
1 November 21, 2002
1 page  
HT27C010
Functional Description
Programming of the HT27C010
When the HT27C010 is delivered, the chip has all
1024K bits in the ²ONE², or HIGH state. ²ZEROs² are
loaded into the HT27C010 through programming.
The programming mode is entered when 12.5±0.2V is ap-
plied to the VPP pin, OE is at VIH, and CE and PGM are
VIL. For programming, the data to be programmed is ap-
plied with 8 bits in parallel to the data pins.
The programming flowchart in Figure 3 shows the fast
interactive programming algorithm. The interactive al-
gorithm reduces programming time by using 30ms to
105ms programming pulses and giving each address
only as many pulses as is necessary in order to reliably
program the data. After each pulse is applied to a given
address, the data in that address is verified. If the data
is not verified, additional pulses are given until it is veri-
fied or until the maximum number of pulses is reached
while sequencing through each address of the
HT27C010. This process is repeated while sequencing
through each address of the HT27C010. This part of
the programming algorithm is done at VCC=6.0V to as-
sure that each EPROM bit is programmed to a suffi-
ciently high threshold voltage. This ensures that all bits
have sufficient margin. After the final address is com-
pleted, the entire EPROM memory is read at
VCC=VPP=5.25±0.25V to verify the entire memory.
Program inhibit mode
Programming of multiple HT27C010 in parallel with dif-
ferent data is also easily accomplished by using the Pro-
gram Inhibit Mode. Except for CE, all like inputs of the
parallel HT27C010 may be common. A TTL low-level
program pulse applied to an HT27C010 CE input with
VPP=12.5±0.2V, PGM LOW, and OE HIGH will program
that HT27C010. A high-level CE input inhibits the
HT27C010 from being programmed.
Program verify mode
Verification should be performed on the programmed
bits to determine whether they were correctly pro-
grammed. The verification should be performed with OE
and CE at VIL, PGM at VIH, and VPP at its programming
voltage.
Auto product identification
The Auto Product Identification mode allows the reading
out of a binary code from an EPROM that will identify its
manufacturer and the type. This mode is intended for
programming to automatically match the device to be
programmed with its corresponding programming algo-
rithm. This mode is functional in the 25°C±5°C ambient
temperature range that is required when programming
the HT27C010.
To activate this mode, the programming equipment
must force 12.0±0.5V on the address line A9 of the
HT27C010. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from VIL to VIH, when A1=VIH. All other address
lines must be held at VIH during Auto Product Identification
mode.
Byte 0 (A0=VIL) represents the manufacturer code, and
byte 1 (A0=VIH), the device code. For HT27C010, these
two identifier bytes are given in the Operation mode truth
table. All identifiers for the manufacturer and device codes
will possess odd parity, with the MSB (DQ7) defined as the
parity bit. When A1=VIL, the HT27C010 will read out the bi-
nary code of 7F, continuation code, to signify the unavail-
ability of manufacturer ID codes.
Read mode
The HT27C010 has two control functions, both of which
must be logically satisfied in order to obtain data at out-
puts. Chip Enable (CE) is the power control and should
be used for device selection. Output Enable (OE) is the
output control and should be used to gate data to the
output pins, independent of device selection. Assuming
that addresses are stable, address access time (tACC) is
equal to the delay from CE to output (tCE). Data is avail-
able at the outputs (tOE) after the falling edge of OE, as-
suming the CE has been LOW and addresses have
been stable for at least tACC-tOE.
Standby mode
The HT27C010 has CMOS standby mode which re-
duces the maximum VCC current to 10mA. It is placed in
CMOS standby when CE is at VCC±0.3V. The
HT27C010 also has a TTL-standby mode which re-
duces the maximum VCC current to 1.0mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state, inde-
pendent of the OE input.
Two-line output control function
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
· Low memory power dissipation
· Assurance that output bus contention will not occur
It is recommended that CE be decoded and used as the
primary device-selection function, while OE be made a
common connection to the READ line from the system
control bus. This assures that all deselected memory
devices are in their low-power standby mode and that
the output pins are only active when data is desired from
a particular memory device.
Rev. 1.10
5 November 21, 2002
5 Page 
32-pin PLCC outline dimensions
4
5
A
B
1 32 29
28
DC
12
13
21
20
K
Symbol
A
B
C
D
E
F
G
H
I
J
K
a
E.
H JG
I
Min.
485
445
585
545
105
¾
15
¾
16
24
8
0°
Dimensions in mil
Nom.
¾
¾
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
HT27C010
Max.
495
455
595
555
115
140
¾
¾
22
32
12
10°
Rev. 1.10
11 November 21, 2002
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet HT27C010.PDF ] | |
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