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PDF HT23C512 Data sheet ( Hoja de datos )

Número de pieza HT23C512
Descripción CMOS 64Kx 8-Bit Mask ROM
Fabricantes Holtek Semiconductor Inc 
Logotipo Holtek Semiconductor Inc Logotipo



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No Preview Available ! HT23C512 Hoja de datos, Descripción, Manual

HT23C512
CMOS 64K×8-Bit Mask ROM
Features
Operating voltage: 2.7V~5.5V
Low power consumption
Operation: 25mA Max. (VCC=5V)
10mA Max. (VCC=3V)
Standby: 30µA Max. (VCC=5V)
10µA Max. (VCC=3V)
Access time:150ns Max. (VCC=5V)
250ns Max. (VCC=3V)
65536×8 bits of mask ROM
Mask options: chip enable CE/CE/OE1/OE1
and output enable OE/OE/NC
TTL compatible inputs and outputs
Tristate outputs
Fully static operation
Package type: 28-pin DIP/SOP
General Description
The HT23C512 is a read-only memory with high
performance CMOS storage device whose 512K
of memory is arranged into 65536 words by 8
bits.
For application flexibility, the chip enable and
output enable control pins can be selected as
active high or active low. This flexibility not only
allows easy interface with most microproces-
sors, but also eliminates bus contention in mul-
tiple bus microprocessor systems. An additional
feature of the HT23C512 is its ability to enter
the standby mode whenever the chip enable
(CE/CE) is inactive, thus reducing current con-
sumption to below 30µA. The combination of
these functions makes the chip suitable for high
density low power memory applications.
Block Diagram
1 24th Aug ’98

1 page




HT23C512 pdf
HT23C512
Functional Description
The HT23C512 has two modes, namely data
read mode and standby mode, controlled by
CE/CE/OE1/OE1 and OE/OE/NC inputs.
Standby mode
The HT23C512 has lower current consumption,
controlled by the chip enable input (CE/CE).
When a low/high level is applied to the CE/CE
input regardless of the output enable
(OE/OE/NC) states, the chip will enter the
standby mode.
Data read mode
When both the chip enable (CE/CE/OE/OE1)
and the output enable (OE/OE/NC) are active,
the chip is in data read mode. Otherwise,
active CE/CE and inactive OE/OE/NC result
in deselect mode. The output will remain in
Hi-Z state.
Timing Diagrams
Propagation delay due to address (CE/CE/OE1/OE1 and OE/OE are active)
Propagation delay due to chip enable and output enable (address valid)
5 24th Aug ’98

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