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PDF HT23C128 Data sheet ( Hoja de datos )
| Número de pieza | HT23C128 | |
| Descripción | CMOS 16Kx 8-Bit Mask ROM | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT23C128
CMOS 16K×8-Bit Mask ROM
Features
• Operating voltage: 2.7V~5.5V
• Low power consumption
– Operation: 25mA Max. (VCC=5V)
10mA Max. (VCC=3V)
– Standby: 30µA Max. (VCC=5V)
10µA Max. (VCC=3V)
• Access time:150ns Max. (VCC=5V)
250ns Max. (VCC=3V)
General Description
The HT23C128 is a read-only memory with
high performance CMOS storage device whose
128K of memory is arranged into 16384 words
by 8 bits.
For application flexibility, the chip enable and
output enable control pins can be selected as
active high or active low. This flexibility not
only allows easy interface with most microproc-
• 16384×8 bits of mask ROM
• Mask options: chip enable CE/CE/OE2/OE2
and output enable OE/OE/NC & OE1/
OE1/NC
• TTL compatible inputs and outputs
• Tristate outputs
• Fully static operation
• Package type: 28-pin DIP/SOP
essors, but also eliminates bus contention in
multiple bus microprocessor systems. An addi-
tional feature of the HT23C128 is its ability to
enter the standby mode whenever the chip en-
able (CE/CE) is inactive, thus reducing current
consumption to below 30µA. The combination of
these functions makes the chip suitable for high
density low power memory applications.
Block Diagram
1 24th Aug ’98
1 page  
HT23C128
Functional Description
The HT23C128 has two modes, namely data
read mode and standby mode, controlled by
CE/CE/OE2/OE2, OE/OE/NC and OE1/OE1/NC
inputs.
• Standby mode
The HT23C128 has lower current consumption,
controlled by the chip enable input (CE/CE).
When a low/high level is applied to the CE/CEB
input regardless of the output enable
(OE/OE/NC and OE1/OE1/NC) states, the chip
will enter the standby mode.
• Data read mode
When both the chip enable (CE/CE/OE2/OE2)
and the output enable (OE/OE/NC and
OE1/OE1/NC) are active, the chip is in data
read mode. Otherwise, active CE/CE and in-
active OE/OE/NC or OE1/OE1/NC result in
deselect mode. The output will remain in Hi-Z
state.
Timing Diagrams
• Propagation delay due to address (CE/CE/OE2/OE2, OE/OE and OE1/OE1 are active)
• Propagation delay due to chip enable and output enable (address valid)
5 24th Aug ’98
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HT23C128.PDF ] | |
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