|
|
PDF HSP50215EVAL Data sheet ( Hoja de datos )
| Número de pieza | HSP50215EVAL | |
| Descripción | DSP Modulator Evaluation Board | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HSP50215EVAL (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
User’s Manual
HSP50215EVAL
January 1999 File Number 4463.3
DSP Modulator Evaluation Board
Evaluation Kit
The HSP50215EVAL Kit provides the necessary tools to
evaluate the HSP50215 Digital Upconverter integrated
circuit and consists of a circuit board and a software
program. The kit is designed for evaluation of Digital
Quadrature Amplitude, FM, and Shaped FM modulation for
IF Communications Applications. The circuit board uses
baseband I and Q data patterns loaded through the 8-bit
parallel interface or the ISAbus interface. Data is output as
either a digital or analog modulated composite IF signal. Up
to four channels can be included in the composite IF output.
To facilitate the use of the board during evaluation, the kit
includes example files for configuration, shaping filters and
input stimulus.
Circuit Board
The Functional Block Diagram illustrates the major functions
of the circuit board. The circuit board is a ISAbus form factor
with 40 pin I/O header/connectors for cascade and output
signals. Baseband test patterns are loaded through the
ISAbus or 8-bit parallel interface. The external Cascade
Input allows expansion of the number of channels in the
composite signal. The board outputs data through both the
RF connector and the 40 pin header. Test connectors are
provided at key signal and control locations in the circuit.
Features
• Multi-Channel Composite IF Output with 1-4 Channels
• Digital or Analog Composite Output
• Baseband Pattern Stimulus Files with Lengths to 64Kbits
• Example Baseband Patterns for BPSK, QPSK, π/4QPSK,
16QAM, FM, GMSK and AWG Noise
• Baseband Patterns Loaded to RAM Via PC ISAbus or
Parallel Port, for Use as Modulator Baseband Data
• DOS Based Configuration/Status Software
Applications
• Evaluation Tool for the Performance of the Digital
UpConverter Configured as PSK, Quadrature Amplitude
(QAM), FM and Shaped FM (MSK) Modulators at Rates
from <1 KBPS to 1.5 MBPS
• Performance Evaluation Tool for Digital Upconversion
• Communications Test Equipment
Functional Block Diagram
40 PIN
CONNECTOR
16
(CASCADE
INPUT)
HSP50215
DIGITAL
16
UPCONVERTER
CHANNEL 4
HSP50215
DIGITAL
16
UPCONVERTER
CHANNEL 3
HSP50215
DIGITAL
UPCONVERTER
16
CHANNEL 2
VCC
FPGA
FPGA
FPGA
-12V
DATA
ADDRESS
RAM
RAM
RAM
INTERFACE BUS
(INPUT DATA PATH AND CONTROL/STATUS INTERFACE)
(OPTIONAL FINAL STAGE BASEBAND DATA INPUT PATH)
8 DATA
ADDRESS
WR
HSP50215
DIGITAL
UPCONVERTER
CHANNEL 1
40 PIN
CONNECTOR
16
14
FPGA
D/A
HI5741
RAM
8 DATA
ADDRESS
WR
VCC
-12V
ADDRESS DECODE
OSC
INTERNAL
CLOCKS
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HSP50215EVAL
2. ___ If a FIR filter design software tool is desired, then
downloading SERINADE from the Intersil Corpora-
tion website into the target directory is recommend-
ed. The web site is found at www.intersil.com and
SERINADE is found under the Products column of
the home page. Select Digital Signal Processing
Products Listing menu item. Select the Develop-
ment Tools menu item. Select the SERINADE menu
item. Download of SERINADE can be done from this
location.
The software must be run from the new target directory
established on the C drive.
Verifying the Control Software and Board Installation
1. ___ On the PC, change the directory to the target direc-
tory where the control software has been installed.
2. ___ Start the program by typing: HSP50215 <Enter>.
3. ___ The MAIN MENU screen will appear. It will look like
Figure 3.
+------------------------------------+
| HSP50215 EVALUATION BOARD SOFTWARE |
+------------------------------------+
MAIN MENU
(0) Board Configuration
(1) Modulator Channel 1 Configuration
(2) Modulator Channel 2 Configuration
(3) Modulator Channel 3 Configuration
(4) Modulator Channel 4 Configuration
(5) Load Configuration File
(6) Save Configuration File
(7) Compute Registers
(8) Configure Board
(9) Test Menu
(10) Exit
ENTER SELECTION: =
(C) Intersil Corporation 1997 Version 1.0
FIGURE 3. MAIN MENU
4. ___ Select item (0) for board configuration and type <En-
ter>. The BOARD INTERFACE MENU will appear as
shown in Figure 4. Use the menu items to change the
default board configuration to match the evaluation
board interface, printer, FPGA addressing and oscil-
lator frequency that you desire. Verify that these set-
tings match the jumper configuration of your
evaluation board.
5. ___ When you have completed making your modifications,
select item (0) and type <Enter> to return to the MAIN
MENU.
6. ___ Select Main Menu item (9) and type <Enter> to enter
the Test Menu. The Test Menu is shown in Figure 5.
7. ___ Select Test Menu Item (6) and type <Enter> to enter
the Test Board submenu.
8. ___ A screen appears that indicates the RAM Address/Da-
ta Bus test results and the HSP50215 data bus test
results. If all the items have passed the test, the board
and software have been properly installed and you
are ready to begin evaluation testing. Skip to step 12.
If any test failed, proceed to step 9.
9. ___ If one of the tests shown on the screen for step 8 did
not pass, then the board jumper configuration should
be reviewed, as it is the most likely culprit.
+-------------------------------------+
| HSP50215 EVALUATION BOARD SOFTWARE |
+------------------------------------+
BOARD INTERFACE MENU
File Name ................ EXAMPLES\EX01QPSK
(1) Interface ...................... ISA
(2) ISA Base Address ............... 0x300
(3) Channel 1 FPGA Address ......... 0
(4) Channel 2 FPGA Address ......... 1
(5) Channel 3 FPGA Address ......... 2
(6) Channel 4 FPGA Address ......... 3
(7) Oscillator Freq ........... 50000000 Hz
(0) Main Menu
ENTER SELECTION:
(C) Intersil Corporation 1997 Version 1.0
FIGURE 4. BOARD INTERFACE SUBMENU
+------------------------------------+
| HSP50215 EVALUATION BOARD SOFTWARE |
+------------------------------------+
TEST MENU
File Name................... EXAMPLES\EX01QPSK
(1) Reset Board
(2) Write to Location While Reset
(3) Read from Location While Reset
(4) Write to Location While Running
(5) Read from Location While Running
(6) Test Board
(0) Main Menu
ENTER SELECTION:
(C) Intersil Corporation 1997 Version 1.0
FIGURE 5. TEST SUBMENU
10. ___ Next, the physical installation should be checked.
11. ___ If the board is properly installed, then a verify that no
ISAbus card addressing contention exists. Steps 9,
10, AND 11 are the leading causes of board test fail-
ure.
5
5 Page 
HSP50215EVAL
Adding the log of the noise bandwidth converts from C/N to
C/No. Subtracting the log of the symbol rate converts from
C/No to Es/No. The modulation factor converts from Es/No
to Eb/No using the equation:
MF = 10LOG[bits/symbol]
This yields MF = 0dB for BPSK, MF = 3.01dB for QPSK, and
MF = 4.77dB for 8 PSK.
An Example Eb/No Calculation
Data File:
QPSKPN, A = 1.0, FSAMP = 128ksym/sec
Noise File:
GN16K, std dev. = 0.25, FSAMP = 400ksamp/sec
Data filter:
IS136B, DC gain = 0.658, NBW = 1.004 x FSAMP
Noise filter:
RRC35A4xDC gain = 0.5, NBW = 0.989xFSAMP
Signal Atten:
20 dB, 26 / 256 = 0.1016
Noise Atten:
14.6 dB, 48 / 256 = 0.1875
Begin by calculating C/NdB:
C/NdB= 10LOG((1.0x0.658x0.1016)2/2(0.25x0.5x0.1875)2)
= 10LOG((4.4693x103)/(1.0986x103))
= 6.094dB
Continue by calculating Eb/No:
Eb/No= 6.094-3.01-10LOG(128,000)+10LOG(0.989x400000)
= 3.084 - 51.072 + 55.973
= 7.98dB
Note that the values for A, standard deviation, DC gains, and
noise bandwidths are found in the file headers of the
example filter and stimulus files provided. When main menu
item (7) is executed, four configuration files are generated,
for the various channels. These files list the hex values for all
of the control registers of the HSP50215. The channel (1, 2,
3, or 4) is indicated by the file suffix. The value of the
multiplier for the attenuators is found in Register 17. This
value, converted to decimal and divided by 256, yields the
linear attenuation multiplier value.
Note that there is an error introduced due to the 8-bit
quantization of the gain control value. The error is small for
attenuations close to 0dB but can be on the order of a tenth
of a dB for attenuations greater than 15dB and as much as
1dB at the bottom of the range.
Exercise #7: PRBS Data
This exercise will configure the board to bypass the filter and
not upconvert, so that the user PRBS data is output. This
configuration is useful for verifying stimulus files that are
short data sequences.
Go to the main menu. Select item (I) and set the following
parameters:
(9)48
(0)Returns to the main menu
This turns channel 1 off.
Select main menu, item (4) and set the following parameters:
(1)0
(7)Stimulus/bpskpn
(8)15
(9)3
(0)Returns to the main menu
This sets the channel 4 stimulus file to be a 15 bit PRBS.
The filter was already set to bypass. The IF is set to 0Hz.
Select main menu item (7) to compute the register values.
Select main menu item (8) to configure the board.
Select submenu item (5) to configure all 4 channels.
Select sumenu item (3) to load both the modulator and
pattern RAM.
When the submenu reappears, the download is complete.
The output waveform should be the input PRBS data
pattern. You should note that this configuration can be used
to verify the maximum input rate by changing the input
sample rate of channel 4 to be < fOSC/16. Varying the input
sample rate will illustrate that with too high of an input
sample rate, the filter does not have sufficient time to
complete an output calculation, and no PRBS pattern is
output. By lowering the input sample rate again, until the
PRBS pattern reappears, the maximum input sample rate
can be determined for your evaluation board/oscillator
combination. Note that a similar process can be used to
determine the maximum input rate of each of the example
filter files, taking care to enter the proper DS and IP values
for each filter as noted in Appendix G - Descriptive File List.
Generating User Configurations
Now that you understand the basics of controlling this
modulator evaluation board, you should be able to edit the
example configuration and stimulus files to obtain the test
figuration you desire. Remember that it is best to begin with
the files that most closely match the desired configuration.
Appendix G - Descriptive File List has a description of these
files.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HSP50215EVAL.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HSP50215EVAL | DSP Modulator Evaluation Board | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |