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PDF HSP48410GC-33 Data sheet ( Hoja de datos )
| Número de pieza | HSP48410GC-33 | |
| Descripción | Histogrammer/Accumulating Buffer | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
HSP48410
May 1999 File Number 3185.2
Histogrammer/Accumulating Buffer
The Intersil HSP48410 is an 84 lead Histogrammer IC
intended for use in image and signal analysis. The on-board
memory is configured as 1024 x 24 array. This translates to
a pixel resolution of 10 bits and an image size of 4k x 4k with
no possibility of overflow.
In addition to Histogramming, the HSP48410 can generate
and store the Cumulative Distribution Function for use in
Histogram Equalization applications. Other capabilities of
the HSP48410 include: Bin Accumulation, Look Up Table,
24-bit Delay Memory, and Delay and Subtract mode.
A Flash Clear pin is available in all modes of operation and
performs a single cycle reset on all locations of the internal
memory array and all internal data paths.
The HSP48410 includes a fully asynchronous interface
which provides a means for communications with a host,
such as a microprocessor. The interface includes dedicated
Read/Write pins and an address port which are
asynchronous to the system clock. This allows random
access of the Histogram Memory Array for analysis or
conditioning of the stored data.
Ordering Information
PART NUMBER
HSP48410JC-33
HSP48410JC-40
HSP48410GC-33
HSP48410GC-40
TEMP.
RANGE (oC)
PACKAGE
0 to 70 84 Ld PLCC
0 to 70 84 Ld PLCC
0 to 70 84 Ld PGA
0 to 70 84 Ld PGA
PKG.
NO.
N84.1.15
N84.1.15
G84.A
G84.A
Block Diagram
Features
• 10-Bit Pixel Data
• 4k x 4k Frame Sizes
• Asynchronous Flash Clear Pin
• Single Cycle Memory Clear
• Fully Asynchronous 16 or 24-Bit Host Interface
• Generates and Stores Cumulative Distribution Function
• Look Up Table Mode
• 1024 x 24-Bit Delay Memory
• 24-Bit Three State I/O Bus
• DC to 40MHz Clock Rate
Applications
• Histogramming
• Histogram Equalization
• Image and Signal Analysis
• Image Enhancement
• RGB Video Delay Line
24
24
DIN0-23
24
PIN0-9
10
IOADD0-9
10
ADDRESS
GENERATOR
1
MUX
HISTOGRAM
MEMORY
ARRAY
DATA
IN
DATA 24
OUT
ADDER
DIO DIO0-23
INTERACE
10 ADDRESS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HSP48410
Functional Description
The Histogrammer is intended for use in signal and image
processing applications. The on-board RAM is 24 bits by
1024 locations. For histogramming, this translates to an
image size of 4k x 4k with 10-bit data. A Functional Block
Diagram of the part is shown in Figure 1.
In addition to histogramming, the HSP48410 will also
perform Histogram Accumulation while feeding the results
back into the memory array. The on-board RAM will then
contain the Cumulative Distribution Function and can be
used for further operation such as histogram equalization.
Other modes are: Bin Accumulate, Look Up Table (LUT),
Delay Memory, and Delay and Subtract. The part can also
be accessed as a 24-bit by 1024 word asynchronous RAM
for preconditioning or reading the results of the histogram.
The Histogrammer can be accessed both synchronously
and asynchronously to the system clock (CLK). It was
designed to be configured asynchronously by a
microprocessor, then switched to a synchronous mode to
process data. The result of the processing can then be read
out synchronously, or the part can be switched to one of the
asynchronous modes so the data may be read out by a
microprocessor. All modes are synchronous except for the
Asynchronous 16 and 24 modes.
A Flash Clear operation allows the user to reset the entire
RAM array and all input and output data paths in a single
cycle.
Histogram Memory Array
The Histogram Memory Array is a 24-bit by 1024 deep RAM.
Depending on the current mode, its input data comes from
either the synchronous input DIN0-23, from the
asynchronous data bus DIO0-23, or from the output of the
adder. The output data goes to the DIO bus in both
synchronous and asynchronous modes.
Address Generator
This section of the circuit determines the source of the RAM
address. In the synchronous modes, the address is taken
from either the output of the counter or PIN0-9. The pixel
input bus is used for Histogram, Bin Accumulate, and
LUT(read) modes. All other synchronous modes, i.e.
Histogram Accumulate, LUT(write), Delay, and Delay and
Subtract use the counter output. The counter is reset on the
first rising edge of CLK after a falling edge on START.
During asynchronous modes, the read and write addresses
to the RAM are taken from the IOADD bus on the falling
edge of the RD and WR signals, respectively.
Adder Input
The Adder Input Control Section contains muxes, registers
and other logic that provide the proper data to the adder. The
configuration of this section is controlled by the output of the
Function Decode Section.
DIO Interface
The DIO Interface Section transfers data between the
Histogrammer and the outside world. In the synchronous
modes, DIO acts as a synchronous output for the data
currently being processed by the chip; RD acts as the output
enable for the DIO bus; WR and IOADD0-9 have no effect.
When either of the Asynchronous modes are selected (16 or
24-bit), the RAM output is passed directly to the DIO bus on
read cycles, and on write cycles, data input on DIO goes to
the RAM input port. In this case, data reads and writes are
controlled by RD, WR and IOADD0-9.
Function Decode
This section provides the signals needed to configure the
part for the different modes. The eight modes are decoded
from FCT0-2 on the rising edge of LD (see Table 1). The
output of this section is a set of signals which control the
path of data through the part.
The mode should only be changed while START is high.
After changing from one mode to another, START must be
clocked high by the rising edge of CLK at least once.
TABLE 1. FUNCTION DECODE
FCT
210
MODE
0 0 0 Histogram
0 0 1 Histogram Accumulate
0 1 0 Delay and Subtract
0 1 1 Look Up Table
1 0 0 Bin Accumulate
1 0 1 Delay Memory
1 1 0 Asynchronous 24
1 1 1 Asynchronous 16
Flash Clear
Flash Clear allows the user to clear the entire RAM with a
single pin. When the FC pin is low, all bits of the RAM and
the data path from the RAM to DIO0-23 are set to zero. The
FC pin is asynchronous with respect to CLK: the reset
begins immediately following a low on this signal. For
synchronous modes, in order to ensure consistent results,
FC should only be active while START is high. For
asynchronous modes, WR must remain inactive while FC
is low.
5
5 Page 
HSP48410
AC Electrical Specifications VCC = 5V ± 5%, TA = 0oC to 70oC (Note 6) (Continued)
-40 (40 MHz) -33 (33 MHz)
PARAMETER
SYMBOL
NOTES
MIN MAX MIN MAX UNITS
FCT0-2 Hold from LD
tFH
0-0-
ns
START Setup to CLK
tSS
12 - 13 -
ns
START Hold from CLK
tSH
0-0-
ns
PIN0-9 Setup Time
tPS
12 - 13 -
ns
PIN0-9 Hold Time
tPH
0-0-
ns
LD Pulse Width
tLL
10 - 12 -
ns
LD Setup to START
tLS Note 7
TCP
TCP -
ns
WR Low
tWL
12 - 15 -
ns
WR High
tWH
12 - 15 -
ns
Address Setup
tAS
13 - 15 -
ns
Address Hold
tAH
1-1-
ns
DIO Setup to WR
tWS
12 - 15 -
ns
DIO Hold from WR
tWH
1-1-
ns
RD Low
tRL
35 - 43 -
ns
RD High
tRH
15 - 17 -
ns
RD Low to DIO Valid
tRD
- 35 - 43
ns
Read/Write Cycle Time
tCY
55 - 65 -
ns
DIO Valid after RD High
tOH Note 8
-0-0
ns
Output Enable Time
tOE Note 9
- 18 - 19
ns
Output Disable Time
tOD Note 8
- 18 - 19
ns
Output Rise Time
tR From 0.8V to 2.0V, Note 8
-6-6
ns
Output Fall Time
tF From 2.0V to 0.8V, Note 8
-6-6
ns
NOTES:
6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK)
= 2.0V, (all others) = 1.5V. Output load circuit with CL = 40pF. Output transition measured at VOH ≥ 1.5V and VOL ≤ 1.5V.
7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START.
8. Characterized upon initial design and after major changes to design and/or process.
9. Transition is measured at ±200mV from steady state voltage with loading as specified in test load circuit with CL = 40pF.
Test Load Circuit
DUT
†INCLUDES STRAY AND JIG CAPACITANCE
CL†
S1
SWITCH S1 OPEN FOR ICCSB AND ICCOP
IOH ± 1.5V
IOL
EQUIVALENT CIRCUIT
11
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| PDF Descargar | [ Datasheet HSP48410GC-33.PDF ] | |
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