PDF ADG333A Data sheet ( Hoja de datos )

Número de pieza	ADG333A
Descripción	Quad SPDT Switch
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet FEATURES 44 V supply maximum ratings VSS to VDD analog signal range Low on resistance (45 Ω max) Low ∆RON (5 Ω max) Low RON match (4 Ω max) Low power dissipation Fast switching times tON < 175 ns tOFF < 145 ns Low leakage currents (5 nA max) Low charge injection (10 pC max) Break-before-make switching action APPLICATIONS Audio and video switching Battery-powered systems Test equipment Communication systems GENERAL DESCRIPTION The ADG333A is a monolithic complementary metal-oxide semiconductor (CMOS) device comprising four independently selectable single-pole, double-throw (SPDT) switches. It is designed on a linear compatible CMOS (LC2MOS) process, which provides low power dissipation yet achieves a high switching speed and a low on resistance. The on-resistance profile is very flat over the full analog input range, ensuring good linearity and low distortion when switching audio signals. High switching speed also makes the device suitable for video signal switching. CMOS construction ensures ultralow power dissipation, making the device ideally suited for portable, battery-powered instruments. When they are on, each switch conducts equally well in both directions and has an input signal range that extends to the power supplies. In the off condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action for use in multiplexer applications. Low charge inject is inherent in the design. Quad SPDT Switch ADG333A FUNCTIONAL BLOCK DIAGRAM S1A D1 S1B IN1 ADG333A IN2 S2B D2 S2A S4A D4 S4B IN4 IN3 S3B D3 S3A SWITCHES SHOWN FOR A LOGIC 1 INPUT Figure 1. PRODUCT HIGHLIGHTS 1. Extended signal range. The ADG333A is fabricated on an enhanced LC2MOS process, giving an increased signal range which extends to the supply rails. 2. Low power dissipation. 3. Low RON. 4. Single-supply operation. For applications in which the analog signal is unipolar, the ADG333A can be operated from a single rail power supply. The device is fully specified with a single 12 V supply. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©1995–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet ADG333A SINGLE SUPPLY VDD = +12 V, VSS = 0 V ± 10%, GND = 0 V, unless otherwise noted.1 Table 2. Parameter ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source Off Leakage IS (OFF) Channel On Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Delay, tOPEN Charge Injection Off Isolation Channel-to-Channel Crosstalk CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD VDD +25°C −40°C to +85°C Unit Test Conditions/Comments 0 V to VDD 35 75 ±0.1 ±0.25 ±0.1 ±0.4 ±3 ±5 V Ω typ Ω max nA typ nA max nA typ nA max VD = 1 V, 10 V, IS = −1 mA VDD = 13.2 V VD = 12.2 V/1 V, VS = 1 V/12.2 V Figure 15 VS = VD = 12.2 V/1 V Figure 16 2.4 V min 0.8 V max ±0.005 ±0.5 µA typ µA max VIN = 0 V or VDD 110 200 100 180 10 5 72 85 12 25 0.05 0.25 0.35 3/30 ns typ ns max ns typ ns max ns min pC typ dB typ dB typ pF typ pF typ mA typ mA max V min/V max RL = 300 Ω, CL = 35 pF; VS = 8 V; Figure 17 RL = 300 Ω, CL = 35 pF; VS = 8 V; Figure 17 RL = 300 Ω, CL = 35 pF; VS = 5 V; Figure 18 VD = 6 V, RD = 0 W, CL = 10 nF; VDD = 12 V, VSS = 0 V; Figure 19 RL = 75 Ω, CL = 5 pF, f = 1 MHz; VS = 1.15 V rms; Figure 20 RL = 75 Ω, CL = 5 pF, f = 1 MHz; VS = 1.15 V rms; Figure 21 VDD = 13.5 V Digital inputs = 0 V or 5 V 1 Temperature range is as follows: B Version: −40°C to +85°C. 2 Guaranteed by design; not subject to production test. Rev. B \| Page 4 of 13 5 Page Data Sheet ADG333A TEST CIRCUITS IDS V1 SD RON = V1/IDS VD Figure 14. On Resistance VDD 0.1µF –10V VS +10V IN VDD SB D SA GND VSS 0.1µF VSS VDD 0.1µF VS VDD SB D SA IN GND VSS 0.1µF VSS RD VD VDD VDD D SA IN GND VSS VSS VDD 0.1µF IS (OFF) A VS SD VD Figure 15. Off Leakage ID (ON) NC A SD VD NC = NO CONNECT Figure 16. On Leakage RL 300Ω VOUT CL 35pF +3V VIN 0V +10V 0V VS –10V Figure 17. Switching Times 50% 50% tOFF tON 50% 50% RL 300Ω VOUT CL 35pF 3V VIN 0V VS VOUT 50% 50% tOPEN Figure 18. Break-Before-Make Delay, tOPEN CL 10nF VOUT 3V VIN 0V VOUT 0V Figure 19. Charge Injection QINJ = CL × ∆VOUT ∆VOUT VDD 0.1µF VDD SD VIN GND VSS VS 0.1µF VSS VOUT RL 75Ω Figure 20. Off Isolation VDD SD 75Ω VS VIN1 VIN2 VOUT SD NC RL 75Ω GND VSS 0.1µF VSS CHANNEL-TO-CHANNEL CROSSTALK 20 × LOG \|VS/VOUT\| Figure 21. Channel-to-Channel Crosstalk Rev. B \| Page 10 of 13 11 Page

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