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PDF ADC7802 Data sheet ( Hoja de datos )
| Número de pieza | ADC7802 | |
| Descripción | Autocalibrating/ 4-Channel/ 12-Bit ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADC7802 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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® ADC7802
Autocalibrating, 4-Channel, 12-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q TOTAL UNADJUSTED ERROR ≤ 1/2LSB
OVER FULL TEMPERATURE RANGE
q FOUR-CHANNEL INPUT MULTIPLEXER
q LOW POWER: 10mW plus Power Down
Mode
q SINGLE SUPPLY: +5V
q FAST CONVERSION TIME: 8.5µs Including
Acquisition
q AUTOCAL: No Offset or Gain Adjust
Required
q UNIPOLAR INPUTS: 0V to 5V
q MICROPROCESSOR-COMPATIBLE
INTERFACE
q INTERNAL SAMPLE/HOLD
DESCRIPTION
The ADC7802 is a monolithic CMOS 12-bit A/D
converter with internal sample/hold and four-channel
multiplexer. An autocalibration cycle, occurring auto-
matically at power on, guarantees a total unadjusted
error within ±1/2LSB over the specified temperature
range, eliminating the need for offset or gain adjust-
ment. The 5V single-supply requirements and stan-
dard CS, RD, and WR control signals make the part
very easy to use in microprocessor applications. Con-
version results are available in two bytes through an 8-
bit three-state output bus.
The ADC7802 is available in a 28-pin plastic DIP and
28-lead PLCC, fully specified for operation over the
industrial –40°C to +85°C temperature range.
CS
A0
Address
Latch and
Calibration
Microcontroller
Clock
Control
RD
A1 Decoder and Memory
Logic
WR
SFR
AIN0
AIN1
AIN2
AIN3
Analog
Multiplexer
Capacitor Array
Sampling ADC
VREF +
VREF –
Three-State
Input/Output
BUSY
8-Bit
Data Bus
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1990 Burr-Brown Corporation
PDS-1050B
Printed in U.S.A. June, 1993
1 page  
TYPICAL PERFORMANCE CURVES
At VA = VD = VREF+ = 5V, VREF– = AGND = 0V, TA = +25°C, unless otherwise specified.
CHANNEL SEPARATION vs FREQUENCY
100
80
Channel AIN3
Channel AIN1
60 Channel AIN0
40
20
0
1 10 100 1000
Frequency of 5Vp-p Signal on Channel AIN2 (kHz)
CODE TRANSITION NOISE
100
75
50
25
0
0 0.25 0.5 0.75 1
Analog Input Voltage – Expected Code Center (LSBs)
SIGNAL/(NOISE + DISTORTION)
vs INPUT FREQUENCY
75
50
25
0
0.1
0.2
0.4 0.6 1
2
Input Frequency (kHz)
4 6 10
INTERNAL CLOCK FREQUENCY
vs TEMPERATURE
1.15
1.1
1.05
RCLOCK = 70kΩ
1
0.95
0.9
–50
–25 0
25 50
Ambient Temperature (°C)
75
100
POWER SUPPLY REJECTION vs FREQUENCY
10
6
4
2
VA VD
1
0.6
0.4
0.2
0.1
0.1
1 10 100
Frequency (kHz)
1000
INTERNAL CLOCK FREQUENCY
vs RCLOCK
10
1
0.1
10
100
RCLOCK (kΩ)
1k
®
5 ADC7802
5 Page 
INPUT PROTECTION
The
input
signal
range
must
not
exceed
±VREF
or
V
A
by
more
than 0.3V.
The analog inputs are internally clamped to VA. To prevent
damage to the ADC7802, the current that can flow into the
inputs must be limited to 20mA. One approach is to use an
external resistor in series with the input filter resistor. For
example, a 1kΩ input resistor allows an overvoltage to 20V
without damage.
REFERENCE INPUTS
A 10µF tantalum capacitor is recommended between VREF+
and V – to insure low source impedance. These capacitors
REF
should be located as close as possible to the ADC7802 to
reduce dynamic errors, since the reference provides packets
of current as the successive approximation steps are carried
out.
V + must not exceed V . Although the accuracy is speci-
REF A
fied with V + = 5V and V – = 0V, the converter can
REF REF
function with VREF+ as low as 2.5V and VREF– as high as 1V.
As long as there is at least a 2.5V difference between V +
REF
and VREF–, the absolute value of errors does not change
significantly, so that accuracy will typically be within
±1LSB. (1/2LSB for a 5V span is 610µV, which is 1LSB for
a 2.5V span.)
The power supply to the reference source needs to be consid-
ered during system design to prevent VREF+ from exceeding
(or overshooting) VA, particularly at power-on. Also, after
power-on, if the reference is not stable within 42,425 clock
cycles, an additional calibration cycle may be needed.
POWER SUPPLIES
The digital and analog power supply lines to the ADC7802
should be bypassed with 10µF tantalum capacitors as close
to the part as possible. Although ADC7802 has excellent
power supply rejection, even for higher frequencies, linear
regulated power supplies are recommended.
Care should be taken to insure that VD does not come up
before VA, or permanent damage to the part may occur.
Figure 10 shows a good supply approach, powering both V
A
and VD from a clean linear supply, with the 10Ω resistor
between V and V insuring that V comes up after V . This
AD
D
A
is also a good method to further isolate the ADC7802 from
digital supplies in a system with significant switching cur-
rents that could degrade the accuracy of conversions.
GROUNDING
To maximize accuracy of the ADC7802, the analog and
digital grounds are not connected internally. These points
should have very low impedance to avoid digital noise
feeding back into the analog ground. The VREF– pin is used as
the reference point for input signals, so it should be con-
nected directly to AGND to reduce potential noise problems.
EXTERNAL CLOCK OPERATION
The circuitry required to drive the ADC7802 clock from an
external source is shown in Figure 11a. The external clock
must provide a 0.8V max for LOW and a 3.5V min for
HIGH, with rise and fall times that do not exceed 200ns. The
minimum pulse width of the external clock must be 200ns.
Synchronizing the conversion clock to an external system
clock is recommended in microprocessor applications to
prevent beat-frequency problems.
Note that the electrical specification tables are based on
using an external 2MHz clock. Typically, the specified
accuracy is maintained for clock frequencies between 0.5
and 2.2MHz.
INTERNAL CLOCK OPERATION
Figure 11b shows how to use the internal clock generating
circuitry. The clock frequency depends only on the value of
the resistor, as shown in “Internal Clock Frequency vs
RCLOCK” in the Typical Performance Curves section.
5V
REF
+
10µF
10µF
+
1 SFR
VA 28
10nF
2 AIN0 AGND 27
3 AIN1
CAL 26
4 AIN2
A1 25
5 AIN3
A0 24
6
10nF
7
8
10nF
9
10
VREF+
VREF–
DGND
VD
D7
CLK
BUSY
HBE
WR
CS
23
22
21
20
19
11 D6
RD 18
12 D5
D0 17
13 D4
D1 16
14 D3
D2 15
10Ω
+5V
+
10µF
FIGURE 10. Power Supply and Reference Decoupling.
74HC-Compatible
Clock Source
CLK
To ADC7802
Pin 23
(a) External Clock Operation
R
+5V
To ADC7802
Pin 23
fCLOCK (in Hz) = 1011/R
(b) Internal Clock Operation
FIGURE 11. Internal Clock Operation.
®
11 ADC7802
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADC7802.PDF ] | |
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